[email protected] (Marc Randolph) wrote in message news:<
[email protected] om>...
> [email protected] (Yu Haiwen) wrote in message news:<[email protected] om>...
> > such a application
> > 40MHz clkin, 20MHz clkdv output and 30MHz clkfx output
> > use clk0 feedback to clkfb
> >
> > can both the clkdv and clkfx's de-skew be guaranteed?
>
> Howdy Yu,
>
> What exactly do you mean by the "clkfx de-skew" portion of your
> question? Considering that there is no fixed phase relationship
> between asynchronous clocks (like your 30 MHz and 40 MHz), what good
> would the de-skew be?
>
> If you post a more complete description of your application, it would
> likely result in multiple responses, possibly each outlining a
> different way to meet your requirements.
>
> Good luck,
>
> Marc
Thanks for your suggestion.
Let me explain the situation.
When we use the DLL function of DCM. All DCM output clocks are
phase-aligned to CLK0 and, therefore, are also phase-aligned to the
input clock.
There's no problem if I only use one of the clkdv output or clkfx
output.
But now I want to use both the tow output clocks, can they still both
phase-aligned to clkin?
I've read the Xilinx answer record 12582, which sugest to use tow DCMs
in series. Though my application is a little different, and I'm
thinking how about using tow DCMs in parallel. Would there be any
improvement?