FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-05-2004, 07:01 PM
Lagudu Sateesh
Posts: n/a
Default DCM Synthesis - Certify Planner Error


I am using DCM component (which is a ISE6.1 coregen synthesizable
module) in top level entity. This top level entity is to be ASIC
prototyped using Certify tool. During certify flow, compilation and
estimation of the flow is running smooth with out any errors. During
partitioning process, i assigned the DCM component and unassigned nets
( which are in 'system unassigned bin' of Partition tree view) to the
user FPGA U1. Then no unassigned components/instances are visible in
'system unassigned bin' of partition tree view. Then during synthesis
process, the following error occurs.

Running board compiler...
Board compiler completed

Board compiler: 0 errors, 0 warnings, 0 notes

Running job planner .....
Job: "Planner" terminated with error status: 3
See log file "~/rev_1/tst.srr"
All instances must be assigned before mapping.
Pleas view log file for a list of unassigned instances .

The .log file does not provide any unsigned instances. But it has
following messages.

Synplicity Planeer, version 6.2/3.2, Build 089R, built Jun 5 2003
nwrver.c:564 Error: vpn: Unknown format character 'ü'
Process took 0.523857 secs real time, 0.42 seconds cputime

Can any body suggest what was the error.

For your information, with out DCM component the entire certify
synthesis flow is perfect i.e. Compilation, estimation, partitioning
and synthesis.

Is the DCM output signals CLK0, CLKDV are depend on the derived clocks
from the synthesis process? If not, what is the bug?

Looking for your valuable suggestions

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
Error in Synplify Pro Synthesis hnjm Verilog 2 05-11-2006 08:58 AM
synthesis error with DC rajan Verilog 4 09-01-2004 10:41 PM
Altera Stratix synthesis error erojr FPGA 2 11-22-2003 04:06 PM

All times are GMT +1. The time now is 11:25 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved