FPGA Central

hey!

i'm using a virtex2 device for implementing a lvds channel link receiver. To
recover the bitclock from the incoming clock- line, i use a dcm with
feedback on clk0.

constant lvds_clk_m : integer := 7 ;
constant lvds_clk_d : integer := 2 ;
constant lvds_phase_mode : string := "FIXED" ;
constant lvds_phase_value : integer := 45 ; -- phase shift value for
place and route
constant lvds_phase_value_udsim : integer := 45 ; -- phase shift value for
unit delay simulation

attribute CLKIN_PERIOD of dcm_3_5_lvds_clk: label is "30" ;
attribute CLKOUT_PHASE_SHIFT of dcm_3_5_lvds_clk: label is
lvds_phase_mode ;
attribute PHASE_SHIFT of dcm_3_5_lvds_clk: label is
lvds_phase_value ;
attribute CLKFX_DIVIDE of dcm_3_5_lvds_clk: label is lvds_clk_d ;
attribute CLKFX_MULTIPLY of dcm_3_5_lvds_clk: label is lvds_clk_m ;
attribute DUTY_CYCLE_CORRECTION of dcm_3_5_lvds_clk: label is "TRUE" ;
attribute DFS_FREQUENCY_MODE of dcm_3_5_lvds_clk: label is "LOW";


the incoming clock is a 33 MHz clk with 57% to 43% dutycycle.

when i disconnect the clock line and plug it in again, the dcm doesn't lock
again. i tried to reset the dcm at the falling edge of the locked pin to
ensure a defined startup, but this seems to have no effect.

now my question: what can i do, to reset the dcm after an interruption of
input clock clkin? is there a specific sequence of actions if have to
execute?

regards

wolfgang

"wolfgang" <[email protected]> wrote in message
news:[email protected]...
> hey!
>
> i'm using a virtex2 device for implementing a lvds channel link receiver.
To
> recover the bitclock from the incoming clock- line, i use a dcm with
> feedback on clk0.
>
> constant lvds_clk_m : integer := 7 ;
> constant lvds_clk_d : integer := 2 ;
> constant lvds_phase_mode : string := "FIXED" ;
> constant lvds_phase_value : integer := 45 ; -- phase shift value
for
> place and route
> constant lvds_phase_value_udsim : integer := 45 ; -- phase shift value for
> unit delay simulation
>
> attribute CLKIN_PERIOD of dcm_3_5_lvds_clk: label is "30" ;
> attribute CLKOUT_PHASE_SHIFT of dcm_3_5_lvds_clk: label is
> lvds_phase_mode ;
> attribute PHASE_SHIFT of dcm_3_5_lvds_clk: label is
> lvds_phase_value ;
> attribute CLKFX_DIVIDE of dcm_3_5_lvds_clk: label is lvds_clk_d ;
> attribute CLKFX_MULTIPLY of dcm_3_5_lvds_clk: label is lvds_clk_m ;
> attribute DUTY_CYCLE_CORRECTION of dcm_3_5_lvds_clk: label is "TRUE" ;
> attribute DFS_FREQUENCY_MODE of dcm_3_5_lvds_clk: label is "LOW";
>
>
> the incoming clock is a 33 MHz clk with 57% to 43% dutycycle.
>
> when i disconnect the clock line and plug it in again, the dcm doesn't
lock
> again. i tried to reset the dcm at the falling edge of the locked pin to
> ensure a defined startup, but this seems to have no effect.
>
> now my question: what can i do, to reset the dcm after an interruption of
> input clock clkin? is there a specific sequence of actions if have to
> execute?
>
> regards
>
> wolfgang
>

Hi,

The point with the DCMs is that you must reset them when the clock returns
or it will fail to lock again. To make life a bit more fun: the lock pin
won't be giving a valid signal when the clock is removed! So no way to use
it for detecting a gone clock. My solution was a small module detecting the
working of the clock. The only constraint to this approach is that you need
a clock that's garanteed to work all the time!

Summary:
- Clock works
- Clock dies
- Clock returns
- Reset DCM
- Wait for "locked" signal to become active
- All is running fine again now

Regards,
Alvin.

Wolfgang,

There is a status bit, CLKIN_STOPPED that is there just for these events. If
you have LOCKED go low, OR CLKIN_STOPPED go high, you will need to reset.

Austin

wolfgang wrote:

> hey!
>
> i'm using a virtex2 device for implementing a lvds channel link receiver. To
> recover the bitclock from the incoming clock- line, i use a dcm with
> feedback on clk0.
>
> constant lvds_clk_m : integer := 7 ;
> constant lvds_clk_d : integer := 2 ;
> constant lvds_phase_mode : string := "FIXED" ;
> constant lvds_phase_value : integer := 45 ; -- phase shift value for
> place and route
> constant lvds_phase_value_udsim : integer := 45 ; -- phase shift value for
> unit delay simulation
>
> attribute CLKIN_PERIOD of dcm_3_5_lvds_clk: label is "30" ;
> attribute CLKOUT_PHASE_SHIFT of dcm_3_5_lvds_clk: label is
> lvds_phase_mode ;
> attribute PHASE_SHIFT of dcm_3_5_lvds_clk: label is
> lvds_phase_value ;
> attribute CLKFX_DIVIDE of dcm_3_5_lvds_clk: label is lvds_clk_d ;
> attribute CLKFX_MULTIPLY of dcm_3_5_lvds_clk: label is lvds_clk_m ;
> attribute DUTY_CYCLE_CORRECTION of dcm_3_5_lvds_clk: label is "TRUE" ;
> attribute DFS_FREQUENCY_MODE of dcm_3_5_lvds_clk: label is "LOW";
>
> the incoming clock is a 33 MHz clk with 57% to 43% dutycycle.
>
> when i disconnect the clock line and plug it in again, the dcm doesn't lock
> again. i tried to reset the dcm at the falling edge of the locked pin to
> ensure a defined startup, but this seems to have no effect.
>
> now my question: what can i do, to reset the dcm after an interruption of
> input clock clkin? is there a specific sequence of actions if have to
> execute?
>
> regards
>
> wolfgang

Wolfgang,

Reset alone does not do it. You have to monitor LOCKED. If you don't
achieve lock within a certain period of time (see data sheets for worst
case) you hit the DCM with a RESET again and go wait for lock one more time.
Repeat as needed.

There are other status bits that will give you more information as to what
is happening with the DCM or its input.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
[email protected]
where
"0_0_0_0_" = "martineu"





"wolfgang" <[email protected]> wrote in message
news:[email protected]...
> hey!
>
> i'm using a virtex2 device for implementing a lvds channel link receiver.
To
> recover the bitclock from the incoming clock- line, i use a dcm with
> feedback on clk0.
>
> constant lvds_clk_m : integer := 7 ;
> constant lvds_clk_d : integer := 2 ;
> constant lvds_phase_mode : string := "FIXED" ;
> constant lvds_phase_value : integer := 45 ; -- phase shift value
for
> place and route
> constant lvds_phase_value_udsim : integer := 45 ; -- phase shift value for
> unit delay simulation
>
> attribute CLKIN_PERIOD of dcm_3_5_lvds_clk: label is "30" ;
> attribute CLKOUT_PHASE_SHIFT of dcm_3_5_lvds_clk: label is
> lvds_phase_mode ;
> attribute PHASE_SHIFT of dcm_3_5_lvds_clk: label is
> lvds_phase_value ;
> attribute CLKFX_DIVIDE of dcm_3_5_lvds_clk: label is lvds_clk_d ;
> attribute CLKFX_MULTIPLY of dcm_3_5_lvds_clk: label is lvds_clk_m ;
> attribute DUTY_CYCLE_CORRECTION of dcm_3_5_lvds_clk: label is "TRUE" ;
> attribute DFS_FREQUENCY_MODE of dcm_3_5_lvds_clk: label is "LOW";
>
>
> the incoming clock is a 33 MHz clk with 57% to 43% dutycycle.
>
> when i disconnect the clock line and plug it in again, the dcm doesn't
lock
> again. i tried to reset the dcm at the falling edge of the locked pin to
> ensure a defined startup, but this seems to have no effect.
>
> now my question: what can i do, to reset the dcm after an interruption of
> input clock clkin? is there a specific sequence of actions if have to
> execute?
>
> regards
>
> wolfgang
>
>
>
>