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  #1 (permalink)  
Old 11-22-2007, 08:19 AM
Guest
 
Posts: n/a
Default DCM with instable clock

In a design, I have to generate several clocks with precisely phase
relationship, I'd like to use DCM. But the clock_input is not stable.
It could possiblely change frequency, even stop for a while. I dont
have input signal to reset DCM. How can I use DCM in this condition?
Or, if don't use DCM, how can I chieve precise phase relationship?

Thank you!
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  #2 (permalink)  
Old 11-22-2007, 07:57 PM
Hal Murray
Guest
 
Posts: n/a
Default Re: DCM with instable clock

In article <[email protected]m>, [email protected] writes:
>In a design, I have to generate several clocks with precisely phase
>relationship, I'd like to use DCM. But the clock_input is not stable.
>It could possiblely change frequency, even stop for a while. I dont
>have input signal to reset DCM. How can I use DCM in this condition?
>Or, if don't use DCM, how can I chieve precise phase relationship?


What sort of frequency range are you interested in?

This isn't "phase" as measured in degrees, but have you
considered an external delay line? If you pick the delays
for the fastest frequency the logic should still work when
the clock slows down. But it might not give you the output
you want.

Have you looked at clock generator chips? Some of them
have multiple outputs at different speeds. You might get
lucky and find something that fits you needs.

In the old days, the do-it-yourself clock generator was
a PAL clocked at twice the highest speed you needed.
(Or a '374 and a few gates.)

--
These are my opinions, not necessarily my employer's. I hate spam.

Reply With Quote
  #3 (permalink)  
Old 11-24-2007, 03:06 AM
Guest
 
Posts: n/a
Default Re: DCM with instable clock

On 11月23日, 上午3时57分, [email protected] (Hal
Murray) wrote:
> In article <[email protected]m>, [email protected] writes:
>
> >In a design, I have to generate several clocks with precisely phase
> >relationship, I'd like to useDCM. But the clock_input is not stable.
> >It could possiblely change frequency, even stop for a while. I dont
> >have input signal to resetDCM. How can I useDCMin this condition?
> >Or, if don't useDCM, how can I chieve precise phase relationship?

>
> What sort of frequency range are you interested in?
>
> This isn't "phase" as measured in degrees, but have you
> considered an external delay line? If you pick the delays
> for the fastest frequency the logic should still work when
> the clock slows down. But it might not give you the output
> you want.
>
> Have you looked at clock generator chips? Some of them
> have multiple outputs at different speeds. You might get
> lucky and find something that fits you needs.
>
> In the old days, the do-it-yourself clock generator was
> a PAL clocked at twice the highest speed you needed.
> (Or a '374 and a few gates.)
>
> --
> These are my opinions, not necessarily my employer's. I hate spam.


Thank you, Murray

It's my fault that I didn't make a clear description.

My whole project is based on a virtex-4 SX55 FPGA, only one
clock_input, frequency up to 300MHz, and may chang to any frequency
slower, but not under my control. So, in FPGA, I have to use some
logic to generate some slower clock in the FPGA to feed internal
logic, which have precisely phase relationship.

As the clock may change frequency while not even notified, how can I
use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with
given phase relationship without DCM? Can I use the LOCKED signal to
reset DCM? Is it reliable?

Thanks!
Reply With Quote
  #4 (permalink)  
Old 11-24-2007, 03:06 AM
Guest
 
Posts: n/a
Default Re: DCM with instable clock

On 11月23日, 上午3时57分, [email protected] (Hal
Murray) wrote:
> In article <[email protected]m>, [email protected] writes:
>
> >In a design, I have to generate several clocks with precisely phase
> >relationship, I'd like to useDCM. But the clock_input is not stable.
> >It could possiblely change frequency, even stop for a while. I dont
> >have input signal to resetDCM. How can I useDCMin this condition?
> >Or, if don't useDCM, how can I chieve precise phase relationship?

>
> What sort of frequency range are you interested in?
>
> This isn't "phase" as measured in degrees, but have you
> considered an external delay line? If you pick the delays
> for the fastest frequency the logic should still work when
> the clock slows down. But it might not give you the output
> you want.
>
> Have you looked at clock generator chips? Some of them
> have multiple outputs at different speeds. You might get
> lucky and find something that fits you needs.
>
> In the old days, the do-it-yourself clock generator was
> a PAL clocked at twice the highest speed you needed.
> (Or a '374 and a few gates.)
>
> --
> These are my opinions, not necessarily my employer's. I hate spam.


Thank you, Murray

It's my fault that I didn't make a clear description.

My whole project is based on a virtex-4 SX55 FPGA, only one
clock_input, frequency up to 300MHz, and may chang to any frequency
slower, but not under my control. So, in FPGA, I have to use some
logic to generate some slower clock in the FPGA to feed internal
logic, which have precisely phase relationship.

As the clock may change frequency while not even notified, how can I
use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with
given phase relationship without DCM? Can I use the LOCKED signal to
reset DCM? Is it reliable?

Thanks!
Reply With Quote
  #5 (permalink)  
Old 11-24-2007, 03:22 AM
Peter Alfke
Guest
 
Posts: n/a
Default Re: DCM with instable clock

On Nov 23, 7:06 pm, [email protected] wrote:
> On 11月23日, 上午3时57分, [email protected] (Hal
>
>
>
> Murray) wrote:
> > In article <[email protected]m>, [email protected] writes:

>
> > >In a design, I have to generate several clocks with precisely phase
> > >relationship, I'd like to useDCM. But the clock_input is not stable.
> > >It could possiblely change frequency, even stop for a while. I dont
> > >have input signal to resetDCM. How can I useDCMin this condition?
> > >Or, if don't useDCM, how can I chieve precise phase relationship?

>
> > What sort of frequency range are you interested in?

>
> > This isn't "phase" as measured in degrees, but have you
> > considered an external delay line? If you pick the delays
> > for the fastest frequency the logic should still work when
> > the clock slows down. But it might not give you the output
> > you want.

>
> > Have you looked at clock generator chips? Some of them
> > have multiple outputs at different speeds. You might get
> > lucky and find something that fits you needs.

>
> > In the old days, the do-it-yourself clock generator was
> > a PAL clocked at twice the highest speed you needed.
> > (Or a '374 and a few gates.)

>
> > --
> > These are my opinions, not necessarily my employer's. I hate spam.

>
> Thank you, Murray
>
> It's my fault that I didn't make a clear description.
>
> My whole project is based on a virtex-4 SX55 FPGA, only one
> clock_input, frequency up to 300MHz, and may chang to any frequency
> slower, but not under my control. So, in FPGA, I have to use some
> logic to generate some slower clock in the FPGA to feed internal
> logic, which have precisely phase relationship.
>
> As the clock may change frequency while not even notified, how can I
> use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with
> given phase relationship without DCM? Can I use the LOCKED signal to
> reset DCM? Is it reliable?
>
> Thanks!


So you have an incoming clock that can be any frequency up to 300 MHz,
and may also stop completely.
Can you run your logic off another, stable oscillator?
A DCM is not the only way to reduce the clock rate: You can use a
simple binary counter for that.

Your question is incomplete. Therefore it is tough to suggest
solutions.
Peter Alfke, Xilinx Applications
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  #6 (permalink)  
Old 11-24-2007, 03:44 AM
Guest
 
Posts: n/a
Default Re: DCM with instable clock

On 11月24日, 上午11时22分, Peter Alfke <[email protected]> wrote:
> On Nov 23, 7:06 pm, [email protected] wrote:
>
>
>
>
>
> > On 11月23日, 上午3时57分, [email protected] (Hal

>
> > Murray) wrote:
> > > In article <[email protected]m>, [email protected] writes:

>
> > > >In a design, I have to generate several clocks with precisely phase
> > > >relationship, I'd like to useDCM. But the clock_input is not stable.
> > > >It could possiblely change frequency, even stop for a while. I dont
> > > >have input signal to resetDCM. How can I useDCMin this condition?
> > > >Or, if don't useDCM, how can I chieve precise phase relationship?

>
> > > What sort of frequency range are you interested in?

>
> > > This isn't "phase" as measured in degrees, but have you
> > > considered an external delay line? If you pick the delays
> > > for the fastest frequency the logic should still work when
> > > the clock slows down. But it might not give you the output
> > > you want.

>
> > > Have you looked at clock generator chips? Some of them
> > > have multiple outputs at different speeds. You might get
> > > lucky and find something that fits you needs.

>
> > > In the old days, the do-it-yourself clock generator was
> > > a PAL clocked at twice the highest speed you needed.
> > > (Or a '374 and a few gates.)

>
> > > --
> > > These are my opinions, not necessarily my employer's. I hate spam.

>
> > Thank you, Murray

>
> > It's my fault that I didn't make a clear description.

>
> > My whole project is based on a virtex-4 SX55 FPGA, only one
> > clock_input, frequency up to 300MHz, and may chang to any frequency
> > slower, but not under my control. So, in FPGA, I have to use some
> > logic to generate some slower clock in the FPGA to feed internal
> > logic, which have precisely phase relationship.

>
> > As the clock may change frequency while not even notified, how can I
> > use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with
> > given phase relationship without DCM? Can I use the LOCKED signal to
> > reset DCM? Is it reliable?

>
> > Thanks!

>
> So you have an incoming clock that can be any frequency up to 300 MHz,
> and may also stop completely.
> Can you run your logic off another, stable oscillator?
> A DCM is not the only way to reduce the clock rate: You can use a
> simple binary counter for that.
>
> Your question is incomplete. Therefore it is tough to suggest
> solutions.
> Peter Alfke, Xilinx Applications- 隐藏被引用文字 -
>
> - 显示引用的文字 -


Hi, Peter

First, I don't have any other oscillators.

Second, as I know, it is tough to achieve phase relationship using
binary counters.
Phase relationship can change dramticly while frequency changs.Do you
have any suggestions?

Third,can I use LOCKED signal to reset DCM? Is it reliable?

Thanks
Reply With Quote
  #7 (permalink)  
Old 11-24-2007, 04:08 AM
Peter Alfke
Guest
 
Posts: n/a
Default Re: DCM with instable clock

On Nov 23, 7:44 pm, [email protected] wrote:
> On 11月24日, 上午11时22分, Peter Alfke <[email protected]> wrote:
>
>
>
> > On Nov 23, 7:06 pm, [email protected] wrote:

>
> > > On 11月23日, 上午3时57分, [email protected] (Hal

>
> > > Murray) wrote:
> > > > In article <[email protected]m>, [email protected] writes:

>
> > > > >In a design, I have to generate several clocks with precisely phase
> > > > >relationship, I'd like to useDCM. But the clock_input is not stable..
> > > > >It could possiblely change frequency, even stop for a while. I dont
> > > > >have input signal to resetDCM. How can I useDCMin this condition?
> > > > >Or, if don't useDCM, how can I chieve precise phase relationship?

>
> > > > What sort of frequency range are you interested in?

>
> > > > This isn't "phase" as measured in degrees, but have you
> > > > considered an external delay line? If you pick the delays
> > > > for the fastest frequency the logic should still work when
> > > > the clock slows down. But it might not give you the output
> > > > you want.

>
> > > > Have you looked at clock generator chips? Some of them
> > > > have multiple outputs at different speeds. You might get
> > > > lucky and find something that fits you needs.

>
> > > > In the old days, the do-it-yourself clock generator was
> > > > a PAL clocked at twice the highest speed you needed.
> > > > (Or a '374 and a few gates.)

>
> > > > --
> > > > These are my opinions, not necessarily my employer's. I hate spam.

>
> > > Thank you, Murray

>
> > > It's my fault that I didn't make a clear description.

>
> > > My whole project is based on a virtex-4 SX55 FPGA, only one
> > > clock_input, frequency up to 300MHz, and may chang to any frequency
> > > slower, but not under my control. So, in FPGA, I have to use some
> > > logic to generate some slower clock in the FPGA to feed internal
> > > logic, which have precisely phase relationship.

>
> > > As the clock may change frequency while not even notified, how can I
> > > use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with
> > > given phase relationship without DCM? Can I use the LOCKED signal to
> > > reset DCM? Is it reliable?

>
> > > Thanks!

>
> > So you have an incoming clock that can be any frequency up to 300 MHz,
> > and may also stop completely.
> > Can you run your logic off another, stable oscillator?
> > A DCM is not the only way to reduce the clock rate: You can use a
> > simple binary counter for that.

>
> > Your question is incomplete. Therefore it is tough to suggest
> > solutions.
> > Peter Alfke, Xilinx Applications- 隐藏被引用文字 -

>
> > - 显示引用的文字 -

>
> Hi, Peter
>
> First, I don't have any other oscillators.
>
> Second, as I know, it is tough to achieve phase relationship using
> binary counters.
> Phase relationship can change dramticly while frequency changs.Do you
> have any suggestions?
>
> Third,can I use LOCKED signal to reset DCM? Is it reliable?
>
> Thanks


If you want meaningful suggestions, you must tell us more about your
design and its constraints.
When you say that you have no continuously running oscillator: You can
buy one for about $1.00.
Peter Alfke
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  #8 (permalink)  
Old 11-24-2007, 08:16 AM
Guest
 
Posts: n/a
Default Re: DCM with instable clock

On 11月24日, 下午12时08分, Peter Alfke <[email protected]> wrote:
> On Nov 23, 7:44 pm, [email protected] wrote:
>
>
>
>
>
> > On 11月24日, 上午11时22分, Peter Alfke <[email protected]> wrote:

>
> > > On Nov 23, 7:06 pm, [email protected] wrote:

>
> > > > On 11月23日, 上午3时57分, [email protected] (Hal

>
> > > > Murray) wrote:
> > > > > In article <[email protected]m>, [email protected] writes:

>
> > > > > >In a design, I have to generate several clocks with precisely phase
> > > > > >relationship, I'd like to useDCM. But the clock_input is not stable.
> > > > > >It could possiblely change frequency, even stop for a while. I dont
> > > > > >have input signal to resetDCM. How can I useDCMin this condition?
> > > > > >Or, if don't useDCM, how can I chieve precise phase relationship?

>
> > > > > What sort of frequency range are you interested in?

>
> > > > > This isn't "phase" as measured in degrees, but have you
> > > > > considered an external delay line? If you pick the delays
> > > > > for the fastest frequency the logic should still work when
> > > > > the clock slows down. But it might not give you the output
> > > > > you want.

>
> > > > > Have you looked at clock generator chips? Some of them
> > > > > have multiple outputs at different speeds. You might get
> > > > > lucky and find something that fits you needs.

>
> > > > > In the old days, the do-it-yourself clock generator was
> > > > > a PAL clocked at twice the highest speed you needed.
> > > > > (Or a '374 and a few gates.)

>
> > > > > --
> > > > > These are my opinions, not necessarily my employer's. I hate spam..

>
> > > > Thank you, Murray

>
> > > > It's my fault that I didn't make a clear description.

>
> > > > My whole project is based on a virtex-4 SX55 FPGA, only one
> > > > clock_input, frequency up to 300MHz, and may chang to any frequency
> > > > slower, but not under my control. So, in FPGA, I have to use some
> > > > logic to generate some slower clock in the FPGA to feed internal
> > > > logic, which have precisely phase relationship.

>
> > > > As the clock may change frequency while not even notified, how can I
> > > > use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with
> > > > given phase relationship without DCM? Can I use the LOCKED signal to
> > > > reset DCM? Is it reliable?

>
> > > > Thanks!

>
> > > So you have an incoming clock that can be any frequency up to 300 MHz,
> > > and may also stop completely.
> > > Can you run your logic off another, stable oscillator?
> > > A DCM is not the only way to reduce the clock rate: You can use a
> > > simple binary counter for that.

>
> > > Your question is incomplete. Therefore it is tough to suggest
> > > solutions.
> > > Peter Alfke, Xilinx Applications- 隐藏被引用文字 -

>
> > > - 显示引用的文字 -

>
> > Hi, Peter

>
> > First, I don't have any other oscillators.

>
> > Second, as I know, it is tough to achieve phase relationship using
> > binary counters.
> > Phase relationship can change dramticly while frequency changs.Do you
> > have any suggestions?

>
> > Third,can I use LOCKED signal to reset DCM? Is it reliable?

>
> > Thanks

>
> If you want meaningful suggestions, you must tell us more about your
> design and its constraints.
> When you say that you have no continuously running oscillator: You can
> buy one for about $1.00.
> Peter Alfke- 隐藏被引用文字 -
>
> - 显示引用的文字 -


I just have one question
Whenever DCM is UNLOCKED, LOCKED signal is low, is that sure?

Thanks
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  #9 (permalink)  
Old 11-24-2007, 04:44 PM
Barry
Guest
 
Posts: n/a
Default Re: DCM with instable clock


>
> I just have one question
> Whenever DCM is UNLOCKED, LOCKED signal is low, is that sure?
>
> Thanks


Not necessarily. At least in a Virtex II DCM, the LOCKED signal is
not valid if the input clock stops. There is another signal in the
STATUS outputs that indicates a loss of input clock, so you have to
AND this with LOCKED to have an indicator of when your DCM is
"working". Other FPGAs' DCMs or PLLs probably work differently than
this, so you need to study the user guide to find out.

Barry
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  #10 (permalink)  
Old 11-26-2007, 03:39 PM
austin
Guest
 
Posts: n/a
Default Re: DCM with instable clock


> I just have one question
> Whenever DCM is UNLOCKED, LOCKED signal is low, is that sure?


Not 'sure', as already mentioned, the status register has flags which
you also need to check:

The most useful is "CLKIN" stopped bit DO(1). There are also other
status bits you may wish to look at ("CLKFB" stopped) to decide if you
should reset the DCM, or not.

http://www.xilinx.com/support/docume...ides/ug070.pdf
(page 64)

Since the DCM is a synchronous state machine, if the clock input stops,
the LOCKED signal will not transition, but the 'stopped' flag will.

Austin


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  #11 (permalink)  
Old 11-28-2007, 09:15 AM
Guest
 
Posts: n/a
Default Re: DCM with instable clock



So, I should use LOCKED and DO(1) to reset my DCM outside of FPGA, or
I can reset DCM inside FPGA using another clock_input. Only these 2
solutions?

Maybe I will do it in my next design, I cannot use DCM these time.

Anyway, thanks, all of you.
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  #12 (permalink)  
Old 11-28-2007, 03:22 PM
austin
Guest
 
Posts: n/a
Default Re: DCM with instable clock

Yes,

Next time, be sure you have a local oscillator--your life will be far
easier.

Austin

[email protected] wrote:
>
> So, I should use LOCKED and DO(1) to reset my DCM outside of FPGA, or
> I can reset DCM inside FPGA using another clock_input. Only these 2
> solutions?
>
> Maybe I will do it in my next design, I cannot use DCM these time.
>
> Anyway, thanks, all of you.

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