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Old 06-23-2005, 06:16 PM
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Default Cyclone Dev. Board, how to set lower clk freq?

I am using Altera's Cyclone EPIC20F4007 Development board and nios I

The problem is that I am unable to set the clk freq. from 50 Mhz to 2
Mhz and get the board working. I have changed the clk setting in th
SOPC to 20 Mhz and also changed the SDRAM_CLK, PLD_CLKOUT and CL
settings to 20 MHZ by factor 2/5. I have also tried different phas
shift settings for SDRAM_CLK(phase shift is -63 degrees in the 5
MHZ, so I supposed it should be-25.2 degrees in the 20 Mhz???), bu
every time when I try to flash some program to the system via NIOS I
IDE I get the next error

sing cable "USB-Blaster [USB-0]", device 1, instance 0x0
Pausing target processor: O
Reading System ID at address 0x021208B8: verifie

Downloading 01000020 ( 0%
Downloading 01010000 (86%
Downloaded 75KB in 0.9s (83.3KB/s

Verifying 01000020 ( 0%
Verify failed
Leaving target processor pause

Could anyone give me good advices to solve this problem?


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