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  #1 (permalink)  
Old 11-07-2007, 08:35 PM
argee
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Default Custom processor developement issues

Hi all,

I'm trying to find a simple way to check the functional correctness of a
custom processor/coprocessor/thingy on an FPGA (I'm kindo new at this).
The core itself is generated automatically (and as such should behave as
planned), so I only need to check if the algorithm that the processor is
supposed to run is working correctly. The processor operates on the data
in it's data memory and I'm looking for a simple way to check that
memory's contents, both during simulation and from the FPGA. Available
tools include Xilinx ISE Webpack + ModelSim XE and Altium Designer +
Nanoboard NB1 (Spartan2). During simulation I wasn't able to access the
memory's internal content (the VHDL variable) from ModelSim so I tried
to verify the design by observing processor/memory comunication which is
tedious and error-prone process (so is using a soft logical analyzer
after implementation). Btw. the implementation uses memories generated
with CoreGenerator if it makes any difference.
So, is there a simple way to run the program on the FPGA and (after the
processor HALTs) read the results on my PC?

TIA

Regards,
RG
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  #2 (permalink)  
Old 11-07-2007, 09:29 PM
Andrew FPGA
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Default Re: Custom processor developement issues

I can't give an exact solution to your problem, but I will briefly
describe the strategy I took in verifying a soft core processor I
modified.

I modified the existing xilnx 8 bit picoblaze soft cpu by adding
several custom instructions including a multiply and turning it into a
pesudo 16 bit processor. I wrote a self-checking testbench in VHDL to
verify a range of processor instructions.
The testbench would:

1) Apply an instruction to the instruction bus ( I had the processor
instantiated in a testbench so that the testbench would feed
instructions).

2) Use modelsim "signal spy" to make key signals inside the cpu
available to my testbench. The most important signals being the data
written to the destination register.

3) Testbench checks the destination register contents and prints an
error if incorrect result.

4) Can make higher level tests my concatenating series of
instructions.

My personal view is that the only time one should be forced into
functional verification on real FPGA hardware is if the simulation is
impractical because
a) the time duration of the simulation takes too long
b) the input required is too complex or can only be generated/accessed
in real hardware.

You can also write non-synthesizable code into your cpu core, that
decodes registers, buses etc and displays text strings in nice
readable format. This helps debugging. Ken Chapman uses this technique
in the picoblaze softcore processor.

Cheers
Andrew

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  #3 (permalink)  
Old 11-07-2007, 10:58 PM
argee
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Default Re: Custom processor developement issues

Andrew FPGA wrote:

> I modified the existing xilnx 8 bit picoblaze soft cpu by adding
> several custom instructions including a multiply and turning it into a
> pesudo 16 bit processor. I wrote a self-checking testbench in VHDL to
> verify a range of processor instructions.


This doesn't directly apply to this particular problem I'm trying to
solve but it sure is a great help for my upcoming hobby projects dealing
with general-purpose cpus (hopefully the next one will have more than 4
instructions .

These processors I'm dealing with are automatically generated
instruction-less microcode-driven thingies (I'm exploring architectural
optimizations), so I hope I'm not going to have to debug their internal
workings. Just want to read the results (and measure performance) for
now and it's a bit frustrating not even being able to do that. *must
learn more*

> 2) Use modelsim "signal spy" to make key signals inside the cpu
> available to my testbench. The most important signals being the data
> written to the destination register.


I will definitely check this out. This "signal spy" seems essential for
verification. Never heard of it before, though. :/

> My personal view is that the only time one should be forced into
> functional verification on real FPGA hardware is if the simulation is
> impractical because
> a) the time duration of the simulation takes too long


Hmmm... So it was wrong of me to assume that some kind of functional
verification in FPGAs is common. I thought there was some simple way to
i.e. read the contents of registers and memories etc. Must be all this
LiveDesign propaganda getting to me...

> You can also write non-synthesizable code into your cpu core, that
> decodes registers, buses etc and displays text strings in nice
> readable format. This helps debugging. Ken Chapman uses this technique
> in the picoblaze softcore processor.


I was thinking about something like that but dismissed it having had
little experience with manually creating testbenches and testing it in
an FPGA seemed way more cool. I think I'll try digging into a manual and
writing a proper testbench that displays the memory content upon
receiving the HALT signal. And assume that the synthesizable HDL +
CoreGen memories combination is functionally equal to the behavioral
model.

Anyways, thanx a bunch! These ideas will be a great help!

Regards,
RG
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  #4 (permalink)  
Old 11-07-2007, 11:33 PM
KJ
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Default Re: Custom processor developement issues


"argee" <[email protected]> wrote in message news:[email protected]
> Hi all,
>
> I'm trying to find a simple way to check the functional correctness of a
> custom processor/coprocessor/thingy on an FPGA (I'm kindo new at this).
> The core itself is generated automatically (and as such should behave as
> planned), so I only need to check if the algorithm that the processor is
> supposed to run is working correctly. The processor operates on the data
> in it's data memory and I'm looking for a simple way to check that
> memory's contents, both during simulation and from the FPGA. Available
> tools include Xilinx ISE Webpack + ModelSim XE and Altium Designer +
> Nanoboard NB1 (Spartan2). During simulation I wasn't able to access the
> memory's internal content (the VHDL variable) from ModelSim so I tried to
> verify the design by observing processor/memory comunication which is
> tedious and error-prone process (so is using a soft logical analyzer after
> implementation). Btw. the implementation uses memories generated with
> CoreGenerator if it makes any difference.
> So, is there a simple way to run the program on the FPGA and (after the
> processor HALTs) read the results on my PC?


I usually add non-synthesizable code that monitors the memory controller and
appends a line to a .CSV file every time a read or write is performed.
Basic template for such logging is...

-- synthesis translate_off
process
if (Reset = '1') then
-- Overwrite existing xxx.csv file with a header line showing
-- what signals will be written
else
if (Memory_Write = '1') then
-- Append to xxx.csv file with the address and data being written
end if;
if (Memory_Read = '1') then
-- Append to xxx.csv file with the address and data being read from.
end if;
end process;
-- synthesis translate_on

You can use standard VHDL text file I/O procedures to do the file stuff. If
you don't have one, you'll need something to convert std_logic_vectors into
strings so that they can be output. I use Ben Cohen's image package to do
that work Google link is
http://www.google.com/search?hl=en&q..._pkg+Ben+Cohen

Formatting the output as a simple comma separated variable file means you
can easily import it into a spreadsheet and do additional work if necessary.


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  #5 (permalink)  
Old 11-07-2007, 11:39 PM
austin
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Default Re: Custom processor developement issues

RG,

There is the ChipScope(tm) core in which you choose to capture events
and data, but unless you know exactly what the "answer" is, then it gets
difficult (you get lost in all the 1's and 0's).

You might like to take a page from manufacturing engineering, and use a
common technique to recognize the "right" answer quickly, which is the
use of "signatures."

A common method is to use a sum, an XOR, or a CRC generator (a running
LFSR on the data) to combine all of the results expected, and reduce
them to a single (short) number of perhaps 16 to 64 bits. Parity alone
is a bit too simple (poor coverage), but multiple parities is sometimes
used (horizontal, vertical, and diagonal).

Then, the expected result is also calculated for the check, and compared
with the actual result.

It isn't 100% (you can find methods which are, but you don't really need
them if the probabilities are low enough, or you do enough tests
generally). A 7 bit CRC will catch 100% of all single, double, etc. up
to 6 bit errors, for example in any data set.

Inside the FPGA, is is a pretty simple matter to place the expected
result, the calculated result, and a comparator, so that all you have to
do is look at one wire/bit/DFF/or LED (marked "answer was good").

Austin
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  #6 (permalink)  
Old 11-07-2007, 11:40 PM
KJ
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Default Re: Custom processor developement issues


"KJ" <[email protected]l.net> wrote in message
news:[email protected]
>

Also add "wait on Reset, Memory_Write, Memory_Read;" to the start of the
process in the previous post.

KJ


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  #7 (permalink)  
Old 11-08-2007, 09:14 AM
argee
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Default Re: Custom processor developement issues

Thank you all!

RG
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