FPGA Groups

FPGA Groups (http://www.fpgacentral.com/group/index.php)
-   FPGA (http://www.fpgacentral.com/group/forumdisplay.php?f=14)
-   -   Crossing clock domain issue at Functional Simulation (http://www.fpgacentral.com/group/showthread.php?t=53156)

Muthu 10-06-2004 12:20 PM

Crossing clock domain issue at Functional Simulation
 
Hi,

It is understood that, HDL functional simulation will not bring out
any Metastability issue with the crossing clock domain paths.

|-----| |------|
---| FF1 |----------| FF2 |---
| | | |
Clk1--|> | Clk2--|> |
|-----| |------|


But, is there any tricky way to Fail the Fucntional simulation for
Crossing clock domain issues.

--
Regards,
Muthu


All times are GMT +1. The time now is 09:59 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved