FPGA Groups - Crossing clock domain issue at Functional Simulation

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Muthu

10-06-2004 12:20 PM

Crossing clock domain issue at Functional Simulation

Hi,

It is understood that, HDL functional simulation will not bring out
any Metastability issue with the crossing clock domain paths.

|-----| |------|
---| FF1 |----------| FF2 |---
| | | |
Clk1--|> | Clk2--|> |
|-----| |------|

But, is there any tricky way to Fail the Fucntional simulation for
Crossing clock domain issues.

--
Regards,
Muthu

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