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  #1 (permalink)  
Old 11-17-2007, 04:00 PM
Didi
Guest
 
Posts: n/a
Default Coolrunner in system programming - XAPP0058 - viable?

I looked at XAPP0058 which describes some algorithms for in system
programming of some Xilinx CPLDs.
It appears that there are enough data to program a XPLA3 device once
I have the binary data I want to program without needing any more
tools/software/hoops_to_jump_through_I_havent_thought_of.
However, given the long history of programming data secrecy (of
not just Xilinx, they only pioneered that, I believe) I would like to
get
a confirmation by someone who has done it that this is actually
possible for the XPLA3.
Can I produce a binary using ABEL or whatever I can find in their
free software (the way this used to be possible using PHDL before
Xilinx bought and made the Coolrunner programming secret) and
program it into their xpla3 parts _without_ using any JTAG
tools/software other than those I make? Would I be able to utilize all
CPLD resources with their free software (as far as producing the
binary
is concerned, that is)?
I am using my own JTAG hardware/software, it runs under DPS,
under which my logic compiler for the Philips coolrunner used to run
(still does, just no parts available). Adapting it to do anything is
not a problem, as long as "anything" is not kept secret.
This may sound overly paranoid, but I do expect all sorts of catches
nowadays not only from Xilinx, hence my question.
IIRC Xilinx had something in the agreement with Philips to support
all
previous customers, but I am not in the mood for legal battles, I just
need a usable CPLD (not one which comes with a PC/MS or whatever
attached to it in order to be written to) without having to do a lot
of
reverse engineering.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
Reply With Quote
  #2 (permalink)  
Old 11-17-2007, 10:43 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:
> I looked at XAPP0058 which describes some algorithms for in system
> programming of some Xilinx CPLDs.
> It appears that there are enough data to program a XPLA3 device once
> I have the binary data I want to program without needing any more
> tools/software/hoops_to_jump_through_I_havent_thought_of.
> However, given the long history of programming data secrecy (of
> not just Xilinx, they only pioneered that, I believe) I would like to
> get
> a confirmation by someone who has done it that this is actually
> possible for the XPLA3.
> Can I produce a binary using ABEL or whatever I can find in their
> free software (the way this used to be possible using PHDL before
> Xilinx bought and made the Coolrunner programming secret) and
> program it into their xpla3 parts _without_ using any JTAG
> tools/software other than those I make? Would I be able to utilize all
> CPLD resources with their free software (as far as producing the
> binary
> is concerned, that is)?
> I am using my own JTAG hardware/software, it runs under DPS,
> under which my logic compiler for the Philips coolrunner used to run
> (still does, just no parts available). Adapting it to do anything is
> not a problem, as long as "anything" is not kept secret.
> This may sound overly paranoid, but I do expect all sorts of catches
> nowadays not only from Xilinx, hence my question.
> IIRC Xilinx had something in the agreement with Philips to support
> all
> previous customers, but I am not in the mood for legal battles, I just
> need a usable CPLD (not one which comes with a PC/MS or whatever
> attached to it in order to be written to) without having to do a lot
> of
> reverse engineering.
>
> Dimiter


If you consider yourself the same as a programmer manufacturer :

My device programmer lists

PZ5032
PZ3032
XC3032XL
XC2C32A

so, that means the algorithms for all of those are published.

-jg


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  #3 (permalink)  
Old 11-17-2007, 11:12 PM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

A few hours of digging later I found out that the JTAG
sequences needed to write to a XPLA3 and Coolrunner-II
are publically available.
However, the JEDEC -> JTAGgable fuse address translation
map is not (I do have that for the Philips Coolrunner,
the bit locations in the JTAG sequence descriptions have
nothing to do with the bit locations in the JEDEC file).
The suggested way is to go through a variety of hoops,
obviously for no other reason than to obscure the fact
that one has to pay them up to translate the bit locations
for me.
Notice this fact is _very_ obscure, I am not sure
many - if any - people realise it, apparently done so
the user would discover that fact when it is too late
(after having designed the part in).

Do people know that? If I am more lucky, has anyone
found the solution to that? (paying up for being allowed
to program a part I have bought is not something I would
consider, this is racket rather than business in my book).

Thanks,

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

On Nov 17, 6:00 pm, Didi <[email protected]> wrote:
> I looked at XAPP0058 which describes some algorithms for in system
> programming of some Xilinx CPLDs.
> It appears that there are enough data to program a XPLA3 device once
> I have the binary data I want to program without needing any more
> tools/software/hoops_to_jump_through_I_havent_thought_of.
> However, given the long history of programming data secrecy (of
> not just Xilinx, they only pioneered that, I believe) I would like to
> get
> a confirmation by someone who has done it that this is actually
> possible for the XPLA3.
> Can I produce a binary using ABEL or whatever I can find in their
> free software (the way this used to be possible using PHDL before
> Xilinx bought and made the Coolrunner programming secret) and
> program it into their xpla3 parts _without_ using any JTAG
> tools/software other than those I make? Would I be able to utilize all
> CPLD resources with their free software (as far as producing the
> binary
> is concerned, that is)?
> I am using my own JTAG hardware/software, it runs under DPS,
> under which my logic compiler for the Philips coolrunner used to run
> (still does, just no parts available). Adapting it to do anything is
> not a problem, as long as "anything" is not kept secret.
> This may sound overly paranoid, but I do expect all sorts of catches
> nowadays not only from Xilinx, hence my question.
> IIRC Xilinx had something in the agreement with Philips to support
> all
> previous customers, but I am not in the mood for legal battles, I just
> need a usable CPLD (not one which comes with a PC/MS or whatever
> attached to it in order to be written to) without having to do a lot
> of
> reverse engineering.
>
> Dimiter
>
> ------------------------------------------------------
> Dimiter Popoff Transgalactic Instruments
>
> http://www.tgi-sci.com
> ------------------------------------------------------


Reply With Quote
  #4 (permalink)  
Old 11-17-2007, 11:17 PM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Hi Jim,

> My device programmer lists
>
> PZ5032
> PZ3032
> XC3032XL
> XC2C32A
>
> so, that means the algorithms for all of those are published.


do you mean there should be all data out there so one can write
what it takes to program a device from a JEDEC file? So far I
fail to find out how (all day), please send some more hint
(also please take my other posting about JEDEC <-> JTAG mapping into
account).

Dimiter

On Nov 18, 12:43 am, Jim Granville <[email protected]>
wrote:
> Didi wrote:
> > I looked at XAPP0058 which describes some algorithms for in system
> > programming of some Xilinx CPLDs.
> > It appears that there are enough data to program a XPLA3 device once
> > I have the binary data I want to program without needing any more
> > tools/software/hoops_to_jump_through_I_havent_thought_of.
> > However, given the long history of programming data secrecy (of
> > not just Xilinx, they only pioneered that, I believe) I would like to
> > get
> > a confirmation by someone who has done it that this is actually
> > possible for the XPLA3.
> > Can I produce a binary using ABEL or whatever I can find in their
> > free software (the way this used to be possible using PHDL before
> > Xilinx bought and made the Coolrunner programming secret) and
> > program it into their xpla3 parts _without_ using any JTAG
> > tools/software other than those I make? Would I be able to utilize all
> > CPLD resources with their free software (as far as producing the
> > binary
> > is concerned, that is)?
> > I am using my own JTAG hardware/software, it runs under DPS,
> > under which my logic compiler for the Philips coolrunner used to run
> > (still does, just no parts available). Adapting it to do anything is
> > not a problem, as long as "anything" is not kept secret.
> > This may sound overly paranoid, but I do expect all sorts of catches
> > nowadays not only from Xilinx, hence my question.
> > IIRC Xilinx had something in the agreement with Philips to support
> > all
> > previous customers, but I am not in the mood for legal battles, I just
> > need a usable CPLD (not one which comes with a PC/MS or whatever
> > attached to it in order to be written to) without having to do a lot
> > of
> > reverse engineering.

>
> > Dimiter

>
> If you consider yourself the same as a programmer manufacturer :
>
> My device programmer lists
>
> PZ5032
> PZ3032
> XC3032XL
> XC2C32A
>
> so, that means the algorithms for all of those are published.
>
> -jg


Reply With Quote
  #5 (permalink)  
Old 11-18-2007, 12:41 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:

> Hi Jim,
>
>
>>My device programmer lists
>>
>>PZ5032
>>PZ3032
>>XC3032XL
>>XC2C32A
>>
>>so, that means the algorithms for all of those are published.

>
>
> do you mean there should be all data out there so one can write
> what it takes to program a device from a JEDEC file? So far I
> fail to find out how (all day), please send some more hint
> (also please take my other posting about JEDEC <-> JTAG mapping into
> account).


Basically, yes. Clearly our programemr supplier (ee tools) has done this.

Mostly they use the JTAG pins and pathway, tho some PLDs also have
extra means to jtag-unlock, which needs more pins.

It means that progamming documents must exist, and be sent to the
programmer manufacturers.

They may not be fully public, but they are not 'closed' either.

So ask Xilinx for the info, explain you are manufacturing device
programmers.

If they prove too hard to work with, you could try Atmel etc
They have appx equivalent devices to the smaller XPLA3

A working device programmer is also not a bad way to reality-check your
work.
eg You can pgm a part, and then confirm you can read it in your system,
and then pgm in your system, and read/save the result, to analyse if
some bits are in the wrong place.

-jg



>
> Dimiter
>
> On Nov 18, 12:43 am, Jim Granville <[email protected]>
> wrote:
>
>>Didi wrote:
>>
>>>I looked at XAPP0058 which describes some algorithms for in system
>>>programming of some Xilinx CPLDs.
>>> It appears that there are enough data to program a XPLA3 device once
>>>I have the binary data I want to program without needing any more
>>>tools/software/hoops_to_jump_through_I_havent_thought_of.
>>> However, given the long history of programming data secrecy (of
>>>not just Xilinx, they only pioneered that, I believe) I would like to
>>>get
>>>a confirmation by someone who has done it that this is actually
>>>possible for the XPLA3.
>>> Can I produce a binary using ABEL or whatever I can find in their
>>>free software (the way this used to be possible using PHDL before
>>>Xilinx bought and made the Coolrunner programming secret) and
>>>program it into their xpla3 parts _without_ using any JTAG
>>>tools/software other than those I make? Would I be able to utilize all
>>>CPLD resources with their free software (as far as producing the
>>>binary
>>>is concerned, that is)?
>>> I am using my own JTAG hardware/software, it runs under DPS,
>>>under which my logic compiler for the Philips coolrunner used to run
>>>(still does, just no parts available). Adapting it to do anything is
>>>not a problem, as long as "anything" is not kept secret.
>>> This may sound overly paranoid, but I do expect all sorts of catches
>>>nowadays not only from Xilinx, hence my question.
>>> IIRC Xilinx had something in the agreement with Philips to support
>>>all
>>>previous customers, but I am not in the mood for legal battles, I just
>>>need a usable CPLD (not one which comes with a PC/MS or whatever
>>>attached to it in order to be written to) without having to do a lot
>>>of
>>>reverse engineering.

>>
>>>Dimiter

>>
>>If you consider yourself the same as a programmer manufacturer :
>>
>>My device programmer lists
>>
>>PZ5032
>>PZ3032
>>XC3032XL
>>XC2C32A
>>
>>so, that means the algorithms for all of those are published.
>>
>>-jg

>
>


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  #6 (permalink)  
Old 11-18-2007, 10:06 AM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

> So ask Xilinx for the info, explain you are manufacturing device
> programmers.
>
> If they prove too hard to work with, you could try Atmel etc
> They have appx equivalent devices to the smaller XPLA3


Well thanks, Jim, sounds encouraging. Have not wasted any time talking
programming data to their support for years, time to try again may be.
I strongly suspect I know what the result will be, though.

> It means that progamming documents must exist, and be sent to the
> programmer manufacturers.


Are you saying you can program a Coolrunner using a non-Xilinx
programmer and a _JEDEC_ file? Without the programmer using
(or asking you to use) some paid Xilinx software to do some
fuse address mapping?
Generally this is the question Xilinx' documents do not
answer (and seem to deliberately obscure).

> A working device programmer is also not a bad way to reality-check your
> work.
> eg You can pgm a part, and then confirm you can read it in your system,
> and then pgm in your system, and read/save the result, to analyse if
> some bits are in the wrong place.


Oh I do not need that, last time I did it for the original Coolrunner
it took me weeks rather than months to do the whole thing having
just the data and a few chips. It totally took me about 3 months
to write a suitable logic compiler (similar - not directly
compatible - to PHDL, but more flexible/powerful, with all the DPS
scripting. macros etc.) and some reverse engineering I had to do
because I did not have all the data (Philips were easier to deal
with than Xilinx - I guess everyone is that - but sent me only
_most_ of the data, omitted a significant part of them...).
Programming a device via JTAG is a lot easier than they make
it sound (and cash in for), one just needs the device documentation.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


On Nov 18, 2:41 am, Jim Granville <[email protected]>
wrote:
> Didi wrote:
> > Hi Jim,

>
> >>My device programmer lists

>
> >>PZ5032
> >>PZ3032
> >>XC3032XL
> >>XC2C32A

>
> >>so, that means the algorithms for all of those are published.

>
> > do you mean there should be all data out there so one can write
> > what it takes to program a device from a JEDEC file? So far I
> > fail to find out how (all day), please send some more hint
> > (also please take my other posting about JEDEC <-> JTAG mapping into
> > account).

>
> Basically, yes. Clearly our programemr supplier (ee tools) has done this.
>
> Mostly they use the JTAG pins and pathway, tho some PLDs also have
> extra means to jtag-unlock, which needs more pins.
>
> It means that progamming documents must exist, and be sent to the
> programmer manufacturers.
>
> They may not be fully public, but they are not 'closed' either.
>
> So ask Xilinx for the info, explain you are manufacturing device
> programmers.
>
> If they prove too hard to work with, you could try Atmel etc
> They have appx equivalent devices to the smaller XPLA3
>
> A working device programmer is also not a bad way to reality-check your
> work.
> eg You can pgm a part, and then confirm you can read it in your system,
> and then pgm in your system, and read/save the result, to analyse if
> some bits are in the wrong place.
>
> -jg
>
>
>
> > Dimiter

>
> > On Nov 18, 12:43 am, Jim Granville <[email protected]>
> > wrote:

>
> >>Didi wrote:

>
> >>>I looked at XAPP0058 which describes some algorithms for in system
> >>>programming of some Xilinx CPLDs.
> >>> It appears that there are enough data to program a XPLA3 device once
> >>>I have the binary data I want to program without needing any more
> >>>tools/software/hoops_to_jump_through_I_havent_thought_of.
> >>> However, given the long history of programming data secrecy (of
> >>>not just Xilinx, they only pioneered that, I believe) I would like to
> >>>get
> >>>a confirmation by someone who has done it that this is actually
> >>>possible for the XPLA3.
> >>> Can I produce a binary using ABEL or whatever I can find in their
> >>>free software (the way this used to be possible using PHDL before
> >>>Xilinx bought and made the Coolrunner programming secret) and
> >>>program it into their xpla3 parts _without_ using any JTAG
> >>>tools/software other than those I make? Would I be able to utilize all
> >>>CPLD resources with their free software (as far as producing the
> >>>binary
> >>>is concerned, that is)?
> >>> I am using my own JTAG hardware/software, it runs under DPS,
> >>>under which my logic compiler for the Philips coolrunner used to run
> >>>(still does, just no parts available). Adapting it to do anything is
> >>>not a problem, as long as "anything" is not kept secret.
> >>> This may sound overly paranoid, but I do expect all sorts of catches
> >>>nowadays not only from Xilinx, hence my question.
> >>> IIRC Xilinx had something in the agreement with Philips to support
> >>>all
> >>>previous customers, but I am not in the mood for legal battles, I just
> >>>need a usable CPLD (not one which comes with a PC/MS or whatever
> >>>attached to it in order to be written to) without having to do a lot
> >>>of
> >>>reverse engineering.

>
> >>>Dimiter

>
> >>If you consider yourself the same as a programmer manufacturer :

>
> >>My device programmer lists

>
> >>PZ5032
> >>PZ3032
> >>XC3032XL
> >>XC2C32A

>
> >>so, that means the algorithms for all of those are published.

>
> >>-jg


Reply With Quote
  #7 (permalink)  
Old 11-18-2007, 07:03 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:
>> So ask Xilinx for the info, explain you are manufacturing device
>>programmers.
>>
>> If they prove too hard to work with, you could try Atmel etc
>>They have appx equivalent devices to the smaller XPLA3

>
>
> Well thanks, Jim, sounds encouraging. Have not wasted any time talking
> programming data to their support for years, time to try again may be.
> I strongly suspect I know what the result will be, though.
>
>
>> It means that progamming documents must exist, and be sent to the
>>programmer manufacturers.

>
>
> Are you saying you can program a Coolrunner using a non-Xilinx
> programmer and a _JEDEC_ file? Without the programmer using
> (or asking you to use) some paid Xilinx software to do some
> fuse address mapping?
> Generally this is the question Xilinx' documents do not
> answer (and seem to deliberately obscure).


Yes. On my EE Tools ChipMAx and TopMAX, I can load a std JED file
(which typically does need Xilinx/Vendor tools to generate
and then I can Pgm Xc2C XCR, XCS Coolrunner devices
( as well as CPLD from Altera, Atmel, Lattice, etc,so they have the
Programming specs from all those suppliers )

The fuse address mapping, is included in the Programming Document,
so the Device programmer handles that
(and does the reverse process, when it reads the CPLD and saves to a JED
file)
It will also vector test, which just needs a simple pin-mapping.

On the documents I've seen, it aligns reasonably well with
the JED - often they vary Pgm block sizes, and round to boundaries,
and security can differ.

>
>> A working device programmer is also not a bad way to reality-check your
>>work.
>> eg You can pgm a part, and then confirm you can read it in your system,
>>and then pgm in your system, and read/save the result, to analyse if
>>some bits are in the wrong place.

>
>
> Oh I do not need that, last time I did it for the original Coolrunner
> it took me weeks rather than months to do the whole thing having
> just the data and a few chips. It totally took me about 3 months
> to write a suitable logic compiler (similar - not directly
> compatible - to PHDL, but more flexible/powerful, with all the DPS
> scripting. macros etc.) and some reverse engineering I had to do
> because I did not have all the data (Philips were easier to deal
> with than Xilinx - I guess everyone is that - but sent me only
> _most_ of the data, omitted a significant part of them...).
> Programming a device via JTAG is a lot easier than they make
> it sound (and cash in for), one just needs the device documentation.


I didn't think you _needed_ it, just that it can be useful to save
time...

-jg

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  #8 (permalink)  
Old 11-18-2007, 09:24 PM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Jim,

> The fuse address mapping, is included in the Programming Document,
> so the Device programmer handles that
> (and does the reverse process, when it reads the CPLD and saves to a JED
> file)
> It will also vector test, which just needs a simple pin-mapping.
>
> On the documents I've seen, it aligns reasonably well with
> the JED - often they vary Pgm block sizes, and round to boundaries,
> and security can differ.


they are cheating somehow.
Their document on Coolrunner-II programming states:

"The Excel fuse map file indicates the bit position of each bit
of fuse data in the ISC Register. Each column in the fuse map
represents a device address. Each row represents a bit in the
ISC Register. The leftmost column is ordinal address 0. The
uppermost row is ISC Register data bit location 0. "

This is pretty much what I have on the original coolruner, the
..xls file which allowed me to do jedec file -> jtag stream.
Not available anywhere from xilinx - I looked pretty hard.

So either the programmer manufacturers have been "party members"
and have been given these data or there is some other cheating
going on.
Can you please verify that you can program a jedec file to
a coolrunner on a PC which does not have the Xilinx software
on it? While being disconected from the net, that is...
If it works, I may apply for party membership at 52 for
the first time, who knows.... :-).

Thanks a lot,

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------



On Nov 18, 9:03 pm, Jim Granville <[email protected]>
wrote:
> Didi wrote:
> >> So ask Xilinx for the info, explain you are manufacturing device
> >>programmers.

>
> >> If they prove too hard to work with, you could try Atmel etc
> >>They have appx equivalent devices to the smaller XPLA3

>
> > Well thanks, Jim, sounds encouraging. Have not wasted any time talking
> > programming data to their support for years, time to try again may be.
> > I strongly suspect I know what the result will be, though.

>
> >> It means that progamming documents must exist, and be sent to the
> >>programmer manufacturers.

>
> > Are you saying you can program a Coolrunner using a non-Xilinx
> > programmer and a _JEDEC_ file? Without the programmer using
> > (or asking you to use) some paid Xilinx software to do some
> > fuse address mapping?
> > Generally this is the question Xilinx' documents do not
> > answer (and seem to deliberately obscure).

>
> Yes. On my EE Tools ChipMAx and TopMAX, I can load a std JED file
> (which typically does need Xilinx/Vendor tools to generate
> and then I can Pgm Xc2C XCR, XCS Coolrunner devices
> ( as well as CPLD from Altera, Atmel, Lattice, etc,so they have the
> Programming specs from all those suppliers )
>
> The fuse address mapping, is included in the Programming Document,
> so the Device programmer handles that
> (and does the reverse process, when it reads the CPLD and saves to a JED
> file)
> It will also vector test, which just needs a simple pin-mapping.
>
> On the documents I've seen, it aligns reasonably well with
> the JED - often they vary Pgm block sizes, and round to boundaries,
> and security can differ.
>
>
>
>
>
> >> A working device programmer is also not a bad way to reality-check your
> >>work.
> >> eg You can pgm a part, and then confirm you can read it in your system,
> >>and then pgm in your system, and read/save the result, to analyse if
> >>some bits are in the wrong place.

>
> > Oh I do not need that, last time I did it for the original Coolrunner
> > it took me weeks rather than months to do the whole thing having
> > just the data and a few chips. It totally took me about 3 months
> > to write a suitable logic compiler (similar - not directly
> > compatible - to PHDL, but more flexible/powerful, with all the DPS
> > scripting. macros etc.) and some reverse engineering I had to do
> > because I did not have all the data (Philips were easier to deal
> > with than Xilinx - I guess everyone is that - but sent me only
> > _most_ of the data, omitted a significant part of them...).
> > Programming a device via JTAG is a lot easier than they make
> > it sound (and cash in for), one just needs the device documentation.

>
> I didn't think you _needed_ it, just that it can be useful to save
> time...
>
> -jg


Reply With Quote
  #9 (permalink)  
Old 11-18-2007, 10:24 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:
> Jim,
>
>
>>The fuse address mapping, is included in the Programming Document,
>>so the Device programmer handles that
>>(and does the reverse process, when it reads the CPLD and saves to a JED
>>file)
>>It will also vector test, which just needs a simple pin-mapping.
>>
>>On the documents I've seen, it aligns reasonably well with
>>the JED - often they vary Pgm block sizes, and round to boundaries,
>>and security can differ.

>
>
> they are cheating somehow.
> Their document on Coolrunner-II programming states:
>
> "The Excel fuse map file indicates the bit position of each bit
> of fuse data in the ISC Register. Each column in the fuse map
> represents a device address. Each row represents a bit in the
> ISC Register. The leftmost column is ordinal address 0. The
> uppermost row is ISC Register data bit location 0. "
>
> This is pretty much what I have on the original coolruner, the
> .xls file which allowed me to do jedec file -> jtag stream.
> Not available anywhere from xilinx - I looked pretty hard.
>
> So either the programmer manufacturers have been "party members"
> and have been given these data


Yes. They don't have the time, or inclination, to reverse engineer !

If Xilinx wants device programmer support, they must provide the info.
(as do all the chip vendors)

> or there is some other cheating going on.
> Can you please verify that you can program a jedec file to
> a coolrunner on a PC which does not have the Xilinx software
> on it? While being disconected from the net, that is...
> If it works, I may apply for party membership at 52 for
> the first time, who knows.... :-).
>
> Thanks a lot,


I'm not sure what you are expecting, the flow IS pretty simple :
[I suspect you are being too paranoid ? ]

eg : I trawl my PC for a Xilinx JED file,
and find this

D:\Xilinx\DesignPaths\Design.JED:

Programmer Jedec Bit Map
Date Extracted: Wed Apr 30 21:16:51 2007
QF25808*
QP56*
QV0*
F0*
X0*
J0 0*
N DEVICE XC2C64-4-CP56*

Note Block 0 *
Note Block 0 ZIA *
L000000 1110110011111111*
L000016 1110101011111111*
<snip>
Note Block 3 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2
RegCom Oe:4 Tm Slw Pu*
L025360 000001111001111100010000001*
L025387 000001111001111100010000001*
L025414 000001111001111100010000001*
L025441 000001111001111110011111100*
L025468 000001111001111101110000001*
L025495 000001111001111110011111100*
L025522 000001111000011100011111100*
L025549 000001111001111110011111100*
L025576 000001111001111110011111100*
L025603 000001111000011100011111100*
L025630 000001111001111110011111100*
L025657 000001111001111110011111100*
L025684 000001111001111110011111100*
L025711 000001111001111110011111100*
L025738 000001111001111110011111100*
L025765 000001111001111110011111100*

Note Globals *
Note Global Clock Mux *
L025792 100*

Note Global Set/Reset Mux *
L025795 00*

Note Global OE Mux *
L025797 11111111*

Note Global Termination *
L025805 0*

Note Input Voltage Standard for IOB *
L025806 1*

Note Output Voltage Standard for IOB *
L025807 1*


Then, on ChipMAX I just Select XC2C64A & File-Open gives this :

-XILINX XC2C64A selected.
-File loading...
-File load success.
-Buffer checksum : 9832h
-File checksum : 9832h
-Blow Count : 24180

and I can see and edit the fuses, by JED number.

So, it is a simple Load process, and no, there is no translation
process needed. The Programming data used by the Pgmr Vendor, handles
all that (and also the converse on read-save-to-JED, as I mentioned )

What I cannot do with Xilinx tools (that I can with Atmel)
is Vector Test the programmed device, but that's a side issue.

-jg

Reply With Quote
  #10 (permalink)  
Old 11-19-2007, 01:13 AM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

> I'm not sure what you are expecting, the flow IS pretty simple :
> [I suspect you are being too paranoid ? ]


Of course I am paranoid - and I do not think I can be nearly
enough that when it comes to xilinx programming data...

> > eg : I trawl my PC for a Xilinx JED file,

> and find this
>
> D:\Xilinx\DesignPaths\Design.JED:
> ...


Are you sure you don't have the xilinx paid software installed
somewhere on that PC? If this is the case we cannot tell whether
there is no fuse address mapping going on behind the scenes
(transparent at user level). They would be less likely to
do that over the net as this would be way easier to catch,
but it would take an unplugged RJ-45 to make sure :-).
Please keep the issue in background and keep me posted if
you stumble across some related news (I seldomly read com.arch.fpga
but a do read pretty often comp.arch.embedded).
I would have tried to talk to some other vendor if anyone
else had a coolrunner-like part (practically 0 static power),
sadly xilinx bought the philips line only to shut it down - and
now I cannot do what I could do while there were Philips devices.
I'll try to ask xilinx support for the .xls document which
translates jedec address <-> jtag_stream_bit_offset; I wonder
how many millions/quarter revenue they'll ask me to make for them
this time before they consider my chance of getting the data (last
time I asked it was $20M/quarter).

Thanks again,

Dimiter

P.S. I keep on wondering how come CPLD/FPGA manufacturers can get
away with selling non-documented devices, if a CPU vendor would try
to sell a processor and supply only a C compiler for it and
no instruction set he would stand no chance (at least in todays
world, not so sure about tomorrows...)

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

On Nov 19, 12:24 am, Jim Granville <[email protected]>
wrote:
> Didi wrote:
> > Jim,

>
> >>The fuse address mapping, is included in the Programming Document,
> >>so the Device programmer handles that
> >>(and does the reverse process, when it reads the CPLD and saves to a JED
> >>file)
> >>It will also vector test, which just needs a simple pin-mapping.

>
> >>On the documents I've seen, it aligns reasonably well with
> >>the JED - often they vary Pgm block sizes, and round to boundaries,
> >>and security can differ.

>
> > they are cheating somehow.
> > Their document on Coolrunner-II programming states:

>
> > "The Excel fuse map file indicates the bit position of each bit
> > of fuse data in the ISC Register. Each column in the fuse map
> > represents a device address. Each row represents a bit in the
> > ISC Register. The leftmost column is ordinal address 0. The
> > uppermost row is ISC Register data bit location 0. "

>
> > This is pretty much what I have on the original coolruner, the
> > .xls file which allowed me to do jedec file -> jtag stream.
> > Not available anywhere from xilinx - I looked pretty hard.

>
> > So either the programmer manufacturers have been "party members"
> > and have been given these data

>
> Yes. They don't have the time, or inclination, to reverse engineer !
>
> If Xilinx wants device programmer support, they must provide the info.
> (as do all the chip vendors)
>
> > or there is some other cheating going on.
> > Can you please verify that you can program a jedec file to
> > a coolrunner on a PC which does not have the Xilinx software
> > on it? While being disconected from the net, that is...
> > If it works, I may apply for party membership at 52 for
> > the first time, who knows.... :-).

>
> > Thanks a lot,

>
> I'm not sure what you are expecting, the flow IS pretty simple :
> [I suspect you are being too paranoid ? ]
>
> eg : I trawl my PC for a Xilinx JED file,
> and find this
>
> D:\Xilinx\DesignPaths\Design.JED:
>
> Programmer Jedec Bit Map
> Date Extracted: Wed Apr 30 21:16:51 2007
> QF25808*
> QP56*
> QV0*
> F0*
> X0*
> J0 0*
> N DEVICE XC2C64-4-CP56*
>
> Note Block 0 *
> Note Block 0 ZIA *
> L000000 1110110011111111*
> L000016 1110101011111111*
> <snip>
> Note Block 3 I/O Macrocell Configuration 27 bits *
> N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2
> RegCom Oe:4 Tm Slw Pu*
> L025360 000001111001111100010000001*
> L025387 000001111001111100010000001*
> L025414 000001111001111100010000001*
> L025441 000001111001111110011111100*
> L025468 000001111001111101110000001*
> L025495 000001111001111110011111100*
> L025522 000001111000011100011111100*
> L025549 000001111001111110011111100*
> L025576 000001111001111110011111100*
> L025603 000001111000011100011111100*
> L025630 000001111001111110011111100*
> L025657 000001111001111110011111100*
> L025684 000001111001111110011111100*
> L025711 000001111001111110011111100*
> L025738 000001111001111110011111100*
> L025765 000001111001111110011111100*
>
> Note Globals *
> Note Global Clock Mux *
> L025792 100*
>
> Note Global Set/Reset Mux *
> L025795 00*
>
> Note Global OE Mux *
> L025797 11111111*
>
> Note Global Termination *
> L025805 0*
>
> Note Input Voltage Standard for IOB *
> L025806 1*
>
> Note Output Voltage Standard for IOB *
> L025807 1*
>
> Then, on ChipMAX I just Select XC2C64A & File-Open gives this :
>
> -XILINX XC2C64A selected.
> -File loading...
> -File load success.
> -Buffer checksum : 9832h
> -File checksum : 9832h
> -Blow Count : 24180
>
> and I can see and edit the fuses, by JED number.
>
> So, it is a simple Load process, and no, there is no translation
> process needed. The Programming data used by the Pgmr Vendor, handles
> all that (and also the converse on read-save-to-JED, as I mentioned )
>
> What I cannot do with Xilinx tools (that I can with Atmel)
> is Vector Test the programmed device, but that's a side issue.
>
> -jg


Reply With Quote
  #11 (permalink)  
Old 11-19-2007, 02:18 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:
>> I'm not sure what you are expecting, the flow IS pretty simple :
>>[I suspect you are being too paranoid ? ]

>
>
> Of course I am paranoid - and I do not think I can be nearly
> enough that when it comes to xilinx programming data...
>
>
>>>eg : I trawl my PC for a Xilinx JED file,

>>
>>and find this
>>
>>D:\Xilinx\DesignPaths\Design.JED:
>>...

>
>
> Are you sure you don't have the xilinx paid software installed
> somewhere on that PC? If this is the case we cannot tell whether
> there is no fuse address mapping going on behind the scenes
> (transparent at user level).


I am sure the system is not that clever. It just loads a JED file, and
programs the device.
You can download the Pgmr file yourself from eetools, and it runs in
demo-mode with no pgmr found, so you can move that around as much as you
like, and load JED files.

They would be less likely to
> do that over the net as this would be way easier to catch,
> but it would take an unplugged RJ-45 to make sure :-).
> Please keep the issue in background and keep me posted if
> you stumble across some related news (I seldomly read com.arch.fpga
> but a do read pretty often comp.arch.embedded).
> I would have tried to talk to some other vendor if anyone
> else had a coolrunner-like part (practically 0 static power),
> sadly xilinx bought the philips line only to shut it down - and
> now I cannot do what I could do while there were Philips devices.


Which part and package are you using, and what specs do you need ?

> I'll try to ask xilinx support for the .xls document which
> translates jedec address <-> jtag_stream_bit_offset; I wonder
> how many millions/quarter revenue they'll ask me to make for them
> this time before they consider my chance of getting the data (last
> time I asked it was $20M/quarter).


They do not have any revenue stipulation for Device Porgrammer
suppliers, Indeed they expect to sell nothing to the vendor, but
they do benefit from the infrastructure of programmers that support the
devices.

-jg

Reply With Quote
  #12 (permalink)  
Old 11-19-2007, 10:05 AM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

> I am sure the system is not that clever. It just loads a JED file, and
> programs the device.
> You can download the Pgmr file yourself from eetools, and it runs in
> demo-mode with no pgmr found, so you can move that around as much as you
> like, and load JED files.


Well I did look for that Chipmax programmer of theirs you mentioned
in your other post and located it at
http://www.eetools.com/index.cfm?fus...y&Product_ID=7
Does not look like a JTAG adaptor to me and there are no Xilinx
devices on it list of supported parts - how can you read/write a
coolrunner
using this?

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


On Nov 19, 4:18 am, Jim Granville <[email protected]>
wrote:
> Didi wrote:
> >> I'm not sure what you are expecting, the flow IS pretty simple :
> >>[I suspect you are being too paranoid ? ]

>
> > Of course I am paranoid - and I do not think I can be nearly
> > enough that when it comes to xilinx programming data...

>
> >>>eg : I trawl my PC for a Xilinx JED file,

>
> >>and find this

>
> >>D:\Xilinx\DesignPaths\Design.JED:
> >>...

>
> > Are you sure you don't have the xilinx paid software installed
> > somewhere on that PC? If this is the case we cannot tell whether
> > there is no fuse address mapping going on behind the scenes
> > (transparent at user level).

>
> I am sure the system is not that clever. It just loads a JED file, and
> programs the device.
> You can download the Pgmr file yourself from eetools, and it runs in
> demo-mode with no pgmr found, so you can move that around as much as you
> like, and load JED files.
>
> They would be less likely to
>
> > do that over the net as this would be way easier to catch,
> > but it would take an unplugged RJ-45 to make sure :-).
> > Please keep the issue in background and keep me posted if
> > you stumble across some related news (I seldomly read com.arch.fpga
> > but a do read pretty often comp.arch.embedded).
> > I would have tried to talk to some other vendor if anyone
> > else had a coolrunner-like part (practically 0 static power),
> > sadly xilinx bought the philips line only to shut it down - and
> > now I cannot do what I could do while there were Philips devices.

>
> Which part and package are you using, and what specs do you need ?
>
> > I'll try to ask xilinx support for the .xls document which
> > translates jedec address <-> jtag_stream_bit_offset; I wonder
> > how many millions/quarter revenue they'll ask me to make for them
> > this time before they consider my chance of getting the data (last
> > time I asked it was $20M/quarter).

>
> They do not have any revenue stipulation for Device Porgrammer
> suppliers, Indeed they expect to sell nothing to the vendor, but
> they do benefit from the infrastructure of programmers that support the
> devices.
>
> -jg


Reply With Quote
  #13 (permalink)  
Old 11-19-2007, 10:39 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:

>>I am sure the system is not that clever. It just loads a JED file, and
>>programs the device.
>>You can download the Pgmr file yourself from eetools, and it runs in
>>demo-mode with no pgmr found, so you can move that around as much as you
>>like, and load JED files.

>
>
> Well I did look for that Chipmax programmer of theirs you mentioned
> in your other post and located it at
> http://www.eetools.com/index.cfm?fus...y&Product_ID=7


Sorry, should have given you a link:
http://www.eetools.com/downloads/ml27h.exe

> Does not look like a JTAG adaptor to me and there are no Xilinx
> devices on it list of supported parts - how can you read/write a
> coolrunner using this?


Download that .exe, unpack, and the device list is under Chipmax2
Their Topmax 2 model also has a back-socket for jtag, but the
ZIF48's also use JTAG.

We have made an adaptor, that takes the ZIF48, and buffers
to a IDC10 header, to match the Atmel CPLD programmer.
So with this, you can ISP pgm, into a cable/pcb.

Programs ATF1502BE much faster via ChipMAX than via the AtmelISP SW.
(and we can vector test via the ZIF48, prior to PCB fab )

Which device did you need ?

-jg




Reply With Quote
  #14 (permalink)  
Old 11-19-2007, 11:49 AM
colin
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

I think your being paranoid to the point of needing some medication!

In the lab, where engineers constantly think "what if?" Xilinx and
others excercise a lot of control, your welcome to argue that it is
too much control. Austin and others will argue with you about the cost
of tech support.

Xilinx make money by selling hundreds of thousands of everything. If
more than .01% of their devices get programmed using their kit I'll be
astounded.

I have sent JEDEC filess all round the world, mainly to the far east,
(unfortunately) and I assure you the manufacturer doesn't have a clue
what the device is or what it does let alone have XILINX webpack
installed.

Right now I've just designed a system with multiple IO modules. I've
routed a JTAG chain through each IO connector so that we can bit bang
JEDEC (or simillar) files and do field upgrade to the CPLDs on every
IO module. We've done it before and it's pretty painless, with no
support from Xilinx.

Colin
Reply With Quote
  #15 (permalink)  
Old 11-19-2007, 04:13 PM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

> Right now I've just designed a system with multiple IO modules. I've
> routed a JTAG chain through each IO connector so that we can bit bang
> JEDEC (or simillar) files and do field upgrade to the CPLDs on every
> IO module. We've done it before and it's pretty painless, with no
> support from Xilinx.


So how do you do the jedec_bit_address -> jtag_stream_bit_offset?
Do you have the .xls files from xilinx which do that for the
Coolrunner?

> I think your being paranoid to the point of needing some medication!


Of course I am. The right medication would come in .xls format,
namely the excel files which map the above mentioned translation.
Unfortunately, no sign of that medicine anywhere on the net
(except being mentioned in their programmer related .pdf files,
to be found there only if you know there is something missing).

I got infected with this paranoya ever since Xilinx bought
the coolrunner and hid the .xls file from me - those which
Philips had provided me with for their generation of devices and
which I have successfully used while such devices were to
be found.

Dimiter

P.S. I am still waiting for "approval" of their web support
in order to be allowed to ask for these files, I'll post my
experience in this thread. Last time I talked to them
they asked me to make $20M revenue/quorter before they would
review my case for handing me the data.... That was about 5
years ago, let me check that again.

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

On Nov 19, 1:49 pm, colin <[email protected]> wrote:
> I think your being paranoid to the point of needing some medication!
>
> In the lab, where engineers constantly think "what if?" Xilinx and
> others excercise a lot of control, your welcome to argue that it is
> too much control. Austin and others will argue with you about the cost
> of tech support.
>
> Xilinx make money by selling hundreds of thousands of everything. If
> more than .01% of their devices get programmed using their kit I'll be
> astounded.
>
> I have sent JEDEC filess all round the world, mainly to the far east,
> (unfortunately) and I assure you the manufacturer doesn't have a clue
> what the device is or what it does let alone have XILINX webpack
> installed.
>
> Right now I've just designed a system with multiple IO modules. I've
> routed a JTAG chain through each IO connector so that we can bit bang
> JEDEC (or simillar) files and do field upgrade to the CPLDs on every
> IO module. We've done it before and it's pretty painless, with no
> support from Xilinx.
>
> Colin


Reply With Quote
  #16 (permalink)  
Old 11-19-2007, 06:49 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:
>
> I got infected with this paranoya ever since Xilinx bought
> the coolrunner and hid the .xls file from me - those which
> Philips had provided me with for their generation of devices and
> which I have successfully used while such devices were to
> be found.


Which device do you target & what specs do you need.
There are other low power CPLDs. The Atmel ATF150xBE's have
very low static Icc, but do not come in all Coolrunner sizes.

-jg


Reply With Quote
  #17 (permalink)  
Old 11-19-2007, 07:56 PM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Hi Jim,

> Sorry, should have given you a link:http://www.eetools.com/downloads/ml27h.exe
>
> > Does not look like a JTAG adaptor to me and there are no Xilinx
> > devices on it list of supported parts - how can you read/write a
> > coolrunner using this?

>
> Download that .exe, unpack, and the device list is under Chipmax2
> Their Topmax 2 model also has a back-socket for jtag, but the
> ZIF48's also use JTAG.


just did all that. Well, not much luck. The only coolrunner device
which appears on the list is the xcr3032xl - which is too small and,
more importantly, discontinued. So at least this programmer
manufacturer
has had only quite limited access to the excel jedec->jtag mapping
files
of xilinx.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

On Nov 19, 12:39 pm, Jim Granville <[email protected]>
wrote:
> Didi wrote:
> >>I am sure the system is not that clever. It just loads a JED file, and
> >>programs the device.
> >>You can download the Pgmr file yourself from eetools, and it runs in
> >>demo-mode with no pgmr found, so you can move that around as much as you
> >>like, and load JED files.

>
> > Well I did look for that Chipmax programmer of theirs you mentioned
> > in your other post and located it at
> >http://www.eetools.com/index.cfm?fus...y&Product_ID=7

>
> Sorry, should have given you a link:http://www.eetools.com/downloads/ml27h.exe
>
> > Does not look like a JTAG adaptor to me and there are no Xilinx
> > devices on it list of supported parts - how can you read/write a
> > coolrunner using this?

>
> Download that .exe, unpack, and the device list is under Chipmax2
> Their Topmax 2 model also has a back-socket for jtag, but the
> ZIF48's also use JTAG.
>
> We have made an adaptor, that takes the ZIF48, and buffers
> to a IDC10 header, to match the Atmel CPLD programmer.
> So with this, you can ISP pgm, into a cable/pcb.
>
> Programs ATF1502BE much faster via ChipMAX than via the AtmelISP SW.
> (and we can vector test via the ZIF48, prior to PCB fab )
>
> Which device did you need ?
>
> -jg


Reply With Quote
  #18 (permalink)  
Old 11-19-2007, 08:01 PM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

On Nov 19, 8:49 pm, Jim Granville <[email protected]>
wrote:
> Didi wrote:
>
> > I got infected with this paranoya ever since Xilinx bought
> > the coolrunner and hid the .xls file from me - those which
> > Philips had provided me with for their generation of devices and
> > which I have successfully used while such devices were to
> > be found.

>
> Which device do you target & what specs do you need.
> There are other low power CPLDs. The Atmel ATF150xBE's have
> very low static Icc, but do not come in all Coolrunner sizes.
>
> -jg


I would be happy if I could do 128 to 512 cell devices - I have
different projects. I could use both the coolrunner-II and
the xpla3 (the latter mostly for the 5V tolerant inputs).
Frankly, if the original coolrunner were available I would
still use it, although it stopped around 100 MHz or so.

I did look at Atmel several times, last time must have
been < a year ago, and I found nothing to switch to, I do
not remember why. I'll give them a look again anyway.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
Reply With Quote
  #19 (permalink)  
Old 11-19-2007, 08:52 PM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

> > Which device do you target & what specs do you need.
> > There are other low power CPLDs. The Atmel ATF150xBE's have
> > very low static Icc, but do not come in all Coolrunner sizes.

>
> > -jg

>
> I would be happy if I could do 128 to 512 cell devices - I have
> different projects. I could use both the coolrunner-II and
> the xpla3 (the latter mostly for the 5V tolerant inputs).
> Frankly, if the original coolrunner were available I would
> still use it, although it stopped around 100 MHz or so.
>
> I did look at Atmel several times, last time must have
> been < a year ago, and I found nothing to switch to, I do
> not remember why. I'll give them a look again anyway.


Just checked that. Well, what they have is ancient stuff - would
have been that even 10 years ago. Their 128 cell device,
which I would have considered - ATF1508ASV(L), draws tens
of milliamps in "standby" mode, has all these pre-coolrunner
various low-power modes to switch to etc., nothing I would
really use in my designs.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


On Nov 19, 10:01 pm, Didi <[email protected]> wrote:
> On Nov 19, 8:49 pm, Jim Granville <[email protected]>
> wrote:
>
> > Didi wrote:

>
> > > I got infected with this paranoya ever since Xilinx bought
> > > the coolrunner and hid the .xls file from me - those which
> > > Philips had provided me with for their generation of devices and
> > > which I have successfully used while such devices were to
> > > be found.

>
> > Which device do you target & what specs do you need.
> > There are other low power CPLDs. The Atmel ATF150xBE's have
> > very low static Icc, but do not come in all Coolrunner sizes.

>
> > -jg

>
> I would be happy if I could do 128 to 512 cell devices - I have
> different projects. I could use both the coolrunner-II and
> the xpla3 (the latter mostly for the 5V tolerant inputs).
> Frankly, if the original coolrunner were available I would
> still use it, although it stopped around 100 MHz or so.
>
> I did look at Atmel several times, last time must have
> been < a year ago, and I found nothing to switch to, I do
> not remember why. I'll give them a look again anyway.
>
> Dimiter
>
> ------------------------------------------------------
> Dimiter Popoff Transgalactic Instruments
>
> http://www.tgi-sci.com
> ------------------------------------------------------


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  #20 (permalink)  
Old 11-19-2007, 09:00 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:
> On Nov 19, 8:49 pm, Jim Granville <[email protected]>
> wrote:
>
>>Didi wrote:
>>
>>
>>>I got infected with this paranoya ever since Xilinx bought
>>>the coolrunner and hid the .xls file from me - those which
>>>Philips had provided me with for their generation of devices and
>>>which I have successfully used while such devices were to
>>>be found.

>>
>>Which device do you target & what specs do you need.
>>There are other low power CPLDs. The Atmel ATF150xBE's have
>>very low static Icc, but do not come in all Coolrunner sizes.
>>
>>-jg

>
>
> I would be happy if I could do 128 to 512 cell devices - I have
> different projects. I could use both the coolrunner-II and
> the xpla3 (the latter mostly for the 5V tolerant inputs).


The Atmel devices top out at 128 macrocells, but you can pack
a little more into a Atmel macrocell.
The new BE family, are uA static devices, in 32/64 MC (released)
and 128MC (soon)

The Lattice ispMACH4000 family go to 256MC in Zero power, and
512 in non-zero power. (IIRC)

In the larger 128/512 macrocell area, CPLDs struggle a little,
and the FPGA Fabric CPLDs are taking over (Altere MAX II,
lattice MachXO, and the Actel Igloo devices are examples.
Igloo are relatively new, but I saw a press release claiming
$1.50[volume] for ~192 macrocell equiv device.

> Frankly, if the original coolrunner were available I would
> still use it, although it stopped around 100 MHz or so.
>
> I did look at Atmel several times, last time must have
> been < a year ago, and I found nothing to switch to, I do
> not remember why. I'll give them a look again anyway.


Yes, 5V compliance is something the CPLD industry is slow to grasp.
CPLDs are general purpose devices that SHOULD be wide-supply complaint,
like Microcontrollers. Power MOSFETS are a common load, and
they are not lowering the drive voltage on those

The uC sector 'gets this', and the new shrink process uC
commonly DO have 5V tolerance, and the better ones, even
allow 5V VccIO for drive to 5V, and 5V ADC's
Many also include on-chip uA regulators (where power budgets allow)

Lattice do have a 'sort-of' 5V spec: they say 5.5V max, but
add this strange qualifier :
"5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed."
[How does one IO, know, or care, what the voltage is on another IO ?]

-jg

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  #21 (permalink)  
Old 11-19-2007, 09:27 PM
Didi
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

> The Atmel devices top out at 128 macrocells, but you can pack
> a little more into a Atmel macrocell.
> The new BE family, are uA static devices, in 32/64 MC (released)
> and 128MC (soon)


Well the fact of the matter is that there is no CPLD on the market
to compete with all the coolrunner parameters at the same time - and
I do use them.
Philips could have taken over the sector with that device easily,
we'll never know what happened behind the scenes so they sold it to
xilinx - who immediately killed the original Philips line which was
great but had leaked out programming information (no other plausible
reason for killing such a good device I can think of).
And now we stand with xilinx having monopoly over the only up-to-date
CPLD on the market, and they will not let you write to it without
revealing your written code to them (oh yeah, they'll swear to god
their software only translates one map to another and I am just
paranoid because I think it is the spyware it actually is - but
ask them _why_ do they keep that jedec -> jtag mapping data secret
and feel free to wait for another century for a plausible answer).

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

On Nov 19, 11:00 pm, Jim Granville <[email protected]>
wrote:
> Didi wrote:
> > On Nov 19, 8:49 pm, Jim Granville <[email protected]>
> > wrote:

>
> >>Didi wrote:

>
> >>>I got infected with this paranoya ever since Xilinx bought
> >>>the coolrunner and hid the .xls file from me - those which
> >>>Philips had provided me with for their generation of devices and
> >>>which I have successfully used while such devices were to
> >>>be found.

>
> >>Which device do you target & what specs do you need.
> >>There are other low power CPLDs. The Atmel ATF150xBE's have
> >>very low static Icc, but do not come in all Coolrunner sizes.

>
> >>-jg

>
> > I would be happy if I could do 128 to 512 cell devices - I have
> > different projects. I could use both the coolrunner-II and
> > the xpla3 (the latter mostly for the 5V tolerant inputs).

>
> The Atmel devices top out at 128 macrocells, but you can pack
> a little more into a Atmel macrocell.
> The new BE family, are uA static devices, in 32/64 MC (released)
> and 128MC (soon)
>
> The Lattice ispMACH4000 family go to 256MC in Zero power, and
> 512 in non-zero power. (IIRC)
>
> In the larger 128/512 macrocell area, CPLDs struggle a little,
> and the FPGA Fabric CPLDs are taking over (Altere MAX II,
> lattice MachXO, and the Actel Igloo devices are examples.
> Igloo are relatively new, but I saw a press release claiming
> $1.50[volume] for ~192 macrocell equiv device.
>
> > Frankly, if the original coolrunner were available I would
> > still use it, although it stopped around 100 MHz or so.

>
> > I did look at Atmel several times, last time must have
> > been < a year ago, and I found nothing to switch to, I do
> > not remember why. I'll give them a look again anyway.

>
> Yes, 5V compliance is something the CPLD industry is slow to grasp.
> CPLDs are general purpose devices that SHOULD be wide-supply complaint,
> like Microcontrollers. Power MOSFETS are a common load, and
> they are not lowering the drive voltage on those
>
> The uC sector 'gets this', and the new shrink process uC
> commonly DO have 5V tolerance, and the better ones, even
> allow 5V VccIO for drive to 5V, and 5V ADC's
> Many also include on-chip uA regulators (where power budgets allow)
>
> Lattice do have a 'sort-of' 5V spec: they say 5.5V max, but
> add this strange qualifier :
> "5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed."
> [How does one IO, know, or care, what the voltage is on another IO ?]
>
> -jg


Reply With Quote
  #22 (permalink)  
Old 11-19-2007, 09:43 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:
>>>Which device do you target & what specs do you need.
>>>There are other low power CPLDs. The Atmel ATF150xBE's have
>>>very low static Icc, but do not come in all Coolrunner sizes.

>>
>>>-jg

>>
>>I would be happy if I could do 128 to 512 cell devices - I have
>>different projects. I could use both the coolrunner-II and
>>the xpla3 (the latter mostly for the 5V tolerant inputs).
>> Frankly, if the original coolrunner were available I would
>>still use it, although it stopped around 100 MHz or so.
>>
>> I did look at Atmel several times, last time must have
>>been < a year ago, and I found nothing to switch to, I do
>>not remember why. I'll give them a look again anyway.

>
>
> Just checked that. Well, what they have is ancient stuff - would
> have been that even 10 years ago. Their 128 cell device,
> which I would have considered - ATF1508ASV(L), draws tens
> of milliamps in "standby" mode, has all these pre-coolrunner
> various low-power modes to switch to etc., nothing I would
> really use in my designs.


For lowest power/new designs, you would choose ATF1508BE
- not sure on the exact uA spec of that,
I think ATF1508BE-7AU100 is now sampling.

See
http://www.embeddedstar.com/weblog/2...tf15xxbe-cpld/

-jg

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  #23 (permalink)  
Old 11-19-2007, 10:11 PM
Antonio Pasini
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Il 18/11/2007 0.12, Didi ha scritto:
> A few hours of digging later I found out that the JTAG
> sequences needed to write to a XPLA3 and Coolrunner-II
> are publically available.
> However, the JEDEC -> JTAGgable fuse address translation
> map is not (I do have that for the Philips Coolrunner,
> the bit locations in the JTAG sequence descriptions have
> nothing to do with the bit locations in the JEDEC file).


Dimitri, I'm not sure I understood what your problem is; do you need to
write your own JTAG programmer routines ?

In last project I did I had to program (or re-program) a CoolrunnerII
(XC2C256) by JTAG with a microcontroller. Xilinx provides all the info
you need in their app notes.

It was not so difficult; in fact, it works so well I'm using that also
on production. Just a second to program a XC2C256, reasonably filled.

1) Tweak the XAPP058 code for your platform; easy, that code is meant to
be "easily" ported.

2) suppose I have my foo.jed file to program (made for XC2C256)

3) use Impact (free download) to translate the jedec in a XSVF binary
file. You can do on GUI by hand, or by makefile as I prefer; syntax is:

impact -batch impact_make_xsvf.cmd

where "impact_make_xsvf.cmd" contains:

setMode -bs
setCable -port xsvf -file "foo.xsvf"
addDevice -p 1 -file "foo.jed"
Program -p 1 -e -v -defaultVersion 0
quit

4) write (or google..) a little utility (BIN2C) to convert your binary
XSVF image file in a C const array in source form, or include it
directly with assembly directives, if any, or whatever you think.

5) the "player" in XAPP058 will erase, blank check, program and verify
your device.


In fact, they did all the hard work for you, and provide also the source
of the jtag "player".

You don't need to pay anyone to do the translation, just use the free
Impact tool. And yes, it works even without network connection (no
spyware, I think!).










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  #24 (permalink)  
Old 11-19-2007, 10:35 PM
rickman
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

On Nov 19, 4:27 pm, Didi <[email protected]> wrote:
> > The Atmel devices top out at 128 macrocells, but you can pack
> > a little more into a Atmel macrocell.
> > The new BE family, are uA static devices, in 32/64 MC (released)
> > and 128MC (soon)

>
> Well the fact of the matter is that there is no CPLD on the market
> to compete with all the coolrunner parameters at the same time - and
> I do use them.


I feel your pain. It is often that I need devices with 5 volt
tolerance. But that makes it difficult to migrate to the finer
processes which lower the cost of devices. Adding extra processing to
retain 5 volt tolerance drives the price back up. I can't say which
of the two is more significant, but it is interesting that many MCU
vendors seem able to produce 5 volt tolerant devices in the newer
processes at *VERY low* prices.

I looked at exactly this issue a bit over a year ago and came up with
the XPLA family and the Lattice parts. Xilinx won't compete on price
with the XPLA line because it is not one of the new lines they are
pushing. I think they literally don't care a hoot about design wins
with older logic. At least the sales people are always pushing the
new stuff even after I have told them why it is not suited (or they
have not been able to tell me how I will be able to get these new
parts in preproduction). Clearly there is a lot of incentive to
salesmen for design wins with the new parts over the old.


> Philips could have taken over the sector with that device easily,
> we'll never know what happened behind the scenes so they sold it to
> xilinx - who immediately killed the original Philips line which was
> great but had leaked out programming information (no other plausible
> reason for killing such a good device I can think of).


Philips and Xilinx have different processes. Xilinx adjusted the
design to suit their manufacturing and to improve it in some ways.
They may not be willing to share detailed info, but I don't think they
would go to the expense of redesigning a chip line just to prevent
users from having "programming information".


> And now we stand with xilinx having monopoly over the only up-to-date
> CPLD on the market, and they will not let you write to it without
> revealing your written code to them (oh yeah, they'll swear to god
> their software only translates one map to another and I am just
> paranoid because I think it is the spyware it actually is - but
> ask them _why_ do they keep that jedec -> jtag mapping data secret
> and feel free to wait for another century for a plausible answer).


You're only paranoid because everyone is out to get you! You don't
have to literally give them your design. You just have to process it
with their software, right? If all else fails, you can do that on a
machine that is not connected anywhere and wipe the disk once you have
taken your data with you. That should make even the CIA happy... well
maybe not the CIA. They would want to reverse engineer the code and
destroy the hard drive along with any non-volatile memory.


Jim,

> > The Atmel devices top out at 128 macrocells, but you can pack
> > a little more into a Atmel macrocell.
> > The new BE family, are uA static devices, in 32/64 MC (released)
> > and 128MC (soon)


I guess these are new devices that weren't out when I looked. Are
they planning anything larger than 128 macrocells? Personally I like
the Lattice parts. They also have some interesting flash FPGA like
devices, but of course they are not zero power.


> > The Lattice ispMACH4000 family go to 256MC in Zero power, and
> > 512 in non-zero power. (IIRC)

>
> > In the larger 128/512 macrocell area, CPLDs struggle a little,
> > and the FPGA Fabric CPLDs are taking over (Altere MAX II,
> > lattice MachXO, and the Actel Igloo devices are examples.
> > Igloo are relatively new, but I saw a press release claiming
> > $1.50[volume] for ~192 macrocell equiv device.


I'm not sure why you say CPLDs are "taking over". 512 macrocell
devices have been around for quite some time. Actually, I think the
Lattice XO flash based FPGA parts are doing a good job of pushing
down, along with the MAX II parts which are FPGA like. Just because
they have flash, does not make them CPLDs in my opinion. These lines
are LUT based and route like FPGAs. I think that makes them much more
usable for the high end of CPLDs, not to mention cheaper!


> > Lattice do have a 'sort-of' 5V spec: they say 5.5V max, but
> > add this strange qualifier :
> > "5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed."
> > [How does one IO, know, or care, what the voltage is on another IO ?]


I asked about this once and they told me it has to do with the leakage
current. You can drive the I/Os above Vdd, but it will draw more
current. Too many at one time and the device can blow. Not totally
unlike multiple I/Os driving LEDs and such. But you can ask your
FAE.
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  #25 (permalink)  
Old 11-19-2007, 11:03 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Coolrunner in system programming - XAPP0058 - viable?

Didi wrote:
>>The Atmel devices top out at 128 macrocells, but you can pack
>>a little more into a Atmel macrocell.
>>The new BE family, are uA static devices, in 32/64 MC (released)
>>and 128MC (soon)

>
>
> Well the fact of the matter is that there is no CPLD on the market
> to compete with all the coolrunner parameters at the same time - and
> I do use them.


Across the size range, you may be right.
But at the highest volume end Atmel and Lattice have good low power
offerings. Actel may start to impact > 128MC CPLDs

> Philips could have taken over the sector with that device easily,
> we'll never know what happened behind the scenes so they sold it to
> xilinx - who immediately killed the original Philips line which was
> great but had leaked out programming information (no other plausible
> reason for killing such a good device I can think of).


My understanding there is the parts were not externally foundry fab'd
and when the plug was pulled on the fab line, that then killed the
product line. (similar problem happened with some Lattice.AMD parts)

Not good for the end customers. - but certainly not a conspiracy,
instead a by-product of some decoupled bean-counter's decisons, and
we have all seen that before !

> And now we stand with xilinx having monopoly over the only up-to-date
> CPLD on the market, and they will not let you write to it without
> revealing your written code to them (oh yeah, they'll swear to god
> their software only translates one map to another and I am just
> paranoid because I think it is the spyware it actually is - but
> ask them _why_ do they keep that jedec -> jtag mapping data secret
> and feel free to wait for another century for a plausible answer).


That is a good question.

Comments Austin ? ( or Jesse? )


-jg

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