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Old 10-22-2003, 02:01 PM
vladimir
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Default Cool test bench generator for testing some devices which describe by Verilog or VHDL

www.hightech-td.com
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Old 10-22-2003, 06:03 PM
Nial Stewart
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Default Re: Cool test bench generator for testing some devices which describe by Verilog or VHDL

I always get an error window with 'File :Not Exist'
when I try to load a source file.

Nial.


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Old 10-23-2003, 04:48 PM
vladimir
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Default Re: Cool test bench generator for testing some devices which describe by Verilog or VHDL

"Nial Stewart" <[email protected]> wrote in message news:<[email protected]> ...
> I always get an error window with 'File :Not Exist'
> when I try to load a source file.
>
> Nial.


I download this program.
This program generates tbench for inout port too.
Interface and help is very good.
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Old 10-24-2003, 12:26 PM
vladimir
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Default Re: Cool test bench generator for testing some devices which describe by Verilog or VHDL

[email protected] (vladimir) wrote in message news:<[email protected] com>...
> www.hightech-td.com


Try download it else.
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