FPGA Central

All-

I am combining 2 .bit files into one .mcs for an XCF16P (XC3S1500-676
and XC3S1000-456). In both cases I've set the Configuration Rate
parameterto 50. It takes 200 msec for DONE to go high -- that sounds
too slow.

Can this be right? Which .bit file takes precedence? Is there
something additional that needs to be set?

-Jeff

Jeff Brower wrote:
> I am combining 2 .bit files into one .mcs for an XCF16P (XC3S1500-676
> and XC3S1000-456). In both cases I've set the Configuration Rate
> parameterto 50. It takes 200 msec for DONE to go high -- that sounds
> too slow.

XCS1500 config is 5,214,784 bits
XCS1000 config is 3,223,488 bits

( 5214784+3223488 bits ) / 50 MHz = 169ms (as a lower bound)

How much faster do you expect it to be?

Alan Nishioka

Alan-

Thanks for your reply.

> XCS1500 config is 5,214,784 bits
> XCS1000 config is 3,223,488 bits
>
> ( 5214784+3223488 bits ) / 50 MHz = 169ms (as a lower bound)
>
> How much faster do you expect it to be?

The first FPGA has a PCI core. We were hoping to boot under 100 msec.
Is there a way to go faster than 50 MHz without resorting to external
clock + INIT gating circuitry?

-Jeff

Jeff Brower wrote:
> The first FPGA has a PCI core. We were hoping to boot under 100 msec.
> Is there a way to go faster than 50 MHz without resorting to external
> clock + INIT gating circuitry?

I don't know. This is one of the reasons I have always used external
pci bridges. But I thought there was more time during pci config.

All I can think of is using two config proms or using parallel config
mode.

Alan Nishioka

Alan Nishioka wrote:
> Jeff Brower wrote:
>
>>The first FPGA has a PCI core. We were hoping to boot under 100 msec.
>>Is there a way to go faster than 50 MHz without resorting to external
>>clock + INIT gating circuitry?
>
>
> I don't know. This is one of the reasons I have always used external
> pci bridges. But I thought there was more time during pci config.
>
> All I can think of is using two config proms or using parallel config
> mode.

On that line, what about one of the 150Mbit Winbond SPI memories, and
a small CPLD to turn it into parallel-config ?

-jg

Jim Granville wrote:

> Alan Nishioka wrote:
>
>> Jeff Brower wrote:
>>
>>> The first FPGA has a PCI core. We were hoping to boot under 100 msec.
>>> Is there a way to go faster than 50 MHz without resorting to external
>>> clock + INIT gating circuitry?
>>
>>
>>
>> I don't know. This is one of the reasons I have always used external
>> pci bridges. But I thought there was more time during pci config.
>>
>> All I can think of is using two config proms or using parallel config
>> mode.
>
>
> On that line, what about one of the 150Mbit Winbond SPI memories, and
oops, that should be 150Mbd, of course....

Alan-

> I don't know. This is one of the reasons I have always used external
> pci bridges. But I thought there was more time during pci config.

I looked up the PCI 2.3 spec, time to first config access is 2^25
clocks, or about 250 msec at 133 MHz. We have customers though who
prize fast turn-on time, so I'm always looking to get under that 100
msec mark.

> All I can think of is using two config proms or using parallel config
> mode.

2 config proms? I wish. The board is jammed -- 16 layers, blind vias,
lots of things like 201s and 2x3 mm oscillators. Pic of the board is
here:

http://www.signalogic.com/sigc5561_ptmc.htm

Parallel config maybe... need to think about that.

-Jeff