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  #1 (permalink)  
Old 07-02-2006, 02:04 PM
gary
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Posts: n/a
Default component instantiation ISE7.1

hi,
Iam trying to instantiate a component from my user_logic_ip.vhd :

signal h:std_logic_vector(0 to 31);
signal k:std_logic_vector(0 to 31);
component inv
port( x: in std_logic_vector(0 to 31);
z: out std_logic_vector(0 to 31));
end component;
begin
call: inv
portmap(h,k);
iam giving these h & k values to slv_reg0 & slv_reg1
because i want to give my input from 'C' and see my output on hype
terminal.
iam using spartan-3 starter kit for download.
In ISE Synthesize is going fine but when iam implementing design followin
warnings & errors are coming:

NgdBuild:889 - Pad net 'k<10>' is not connected to an external port in
this design. A new port 'k<10>' has been added and is connected t
this
signal.
WARNING:NgdBuild:889 - Pad net 'k<4>' is not connected to an external por
in
this design. A new port 'k<4>' has been added and is connected t
this
signal.
WARNING:NgdBuild:889 - Pad net 'k<6>' is not connected to an external por
in
this design. A new port 'k<6>' has been added and is connected t
this
signal.

---------------------all k<0> to k<31>------------------------

ERROR:
NgdBuild:809 - output pad net 'k<10>' has an illegal load:
pin I2 on block IP2Bus_Data<10>1 with type LUT3
ERROR:NgdBuild:809 - output pad net 'k<4>' has an illegal load:
pin I2 on block IP2Bus_Data<4>1 with type LUT3
ERROR:NgdBuild:809 - output pad net 'k<6>' has an illegal load:
pin I2 on block IP2Bus_Data<6>1 with type LUT3

--------------------all k<0> to k<31>------------------------

i dont understand what these errors mean......
can anybody help me...........
regards
gary



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  #2 (permalink)  
Old 07-02-2006, 03:35 PM
MM
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Posts: n/a
Default Re: component instantiation ISE7.1

Could you upload your vhdl file to somewhere?

/Mikhail



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  #3 (permalink)  
Old 07-03-2006, 01:25 AM
gary
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Posts: n/a
Default Re: component instantiation ISE7.1

>Could you upload your vhdl file to somewhere?
>
>/Mikhail
>

u want to see the instantiated file it is just a inverter ...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inverter is
Port ( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end inverter;

architecture Behavioral of inverter is

begin
t<=not s;

end Behavioral;

this inverter is called in my userip.vhd file .......

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic

------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 t
C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 t
C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 t
C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 2);
signal slv_reg_read_select : std_logic_vector(0 to 2);
signal slv_ip2bus_data : std_logic_vector(0 t
C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal h : std_logic_vector(0 to 31);
signal k : std_logic_vector(0 to 31);
component inverter
port( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end component;

attribute box_type : string;
attribute box_type of inverter : component is "black_box";

begin

we: inverter
port map(h,k);

/gary

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  #4 (permalink)  
Old 07-03-2006, 07:33 PM
MM
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

"gary" <[email protected]> wrote in message
news:[email protected]
> u want to see the instantiated file it is just a inverter ...


No, I wanted to see your userip.vhd, in particular what you are doing with h
and k, how they get assigned, etc.

Does the implementation work with the original (wizard generated)
userip.vhd?

/Mikhail


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  #5 (permalink)  
Old 07-04-2006, 01:04 AM
gary
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Posts: n/a
Default Re: component instantiation ISE7.1

>"gary" <[email protected]> wrote in message
>news:[email protected]
>> u want to see the instantiated file it is just a inverter ...

>
>No, I wanted to see your userip.vhd, in particular what you are doin

with h
>and k, how they get assigned, etc.
>
>Does the implementation work with the original (wizard generated)
>userip.vhd?
>
>/Mikhail
>
>hi,

Iam giving the h,k values to the regesters (slv_reg0,slv_reg1), s
that i can throw the input value from the 'C' code to the inverter & se
the output of the inverter value on the hyper terminal.


Following is my user_ip.vhd file..
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for use
logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for use
logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for use
logic
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Ack -- IP to Bus acknowledgement
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
------------------------------------------------------------------------------

entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 3
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 t
C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 t
C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 t
C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 t
C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 t
C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic

------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 2);
signal slv_reg_read_select : std_logic_vector(0 to 2);
signal slv_ip2bus_data : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal h : std_logic_vector(0 to 31);
signal k : std_logic_vector(0 to 31);
component inverter
port( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end component;

begin

we: inverter
port map(h,k);

--USER logic implementation added here

------------------------------------------
-- Example code to read/write user logic slave model s/w accessible
registers
--
-- Note:
-- The example code presented here is to show you one way of
reading/writing
-- software accessible registers implemented in the user logic slave
model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
-- to one software accessible register by the top level template. For
example,
-- if you have four 32 bit software accessible registers in the user
logic, you
-- are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE or Memory Mapped
-- Bus2IP_RdCE Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_select <= Bus2IP_WrCE(0 to 2);
slv_reg_read_select <= Bus2IP_RdCE(0 to 2);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or
Bus2IP_WrCE(2);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or
Bus2IP_RdCE(2);

-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
else
case slv_reg_write_select is
when "100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "010" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "001" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
slv_reg1,h,k,slv_reg2 ) is
begin

case slv_reg_read_select is
when "100" => slv_ip2bus_data <= h;
when "010" => slv_ip2bus_data <= k;
when "001" => slv_ip2bus_data <= slv_reg2;
when others => slv_ip2bus_data <= (others => '0');
end case;

end process SLAVE_REG_READ_PROC;

------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data;

IP2Bus_Ack <= slv_write_ack or slv_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';

end IMP;

//regards
//gary




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  #6 (permalink)  
Old 07-04-2006, 05:45 AM
MM
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

Gary,

h doesn't have a source in your code. You need to add something like this:
h <= slv_reg0;
Or just use slv_reg0 instead of h as input to your inverter and in the read
process.

/Mikhail



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  #7 (permalink)  
Old 07-06-2006, 02:07 AM
gary
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

>Gary,
>
>h doesn't have a source in your code. You need to add something lik

this:
>h <= slv_reg0;
>Or just use slv_reg0 instead of h as input to your inverter and in th

read
>process.
>
>/Mikhail
>hey,

In user_ip.vhd file i used the following instantation in user logi
implementation
h<=slv_reg0;
k<=slv_reg1;
again synthesis is going on well but the same errors what i posted in m
first message are coming again.

And in the second method i disabled h & k signals directly i assigned
portmap(slv_reg0,slv_reg1) in following way
------------
component inverter
port( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end component;

---attribute box_type : string;
--attribute box_type of inverter : component is "black_box";

begin

we: inverter
port map(slv_reg0,slv_reg1);
----------------------------
while synthesis following errors are generated....

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal <slv_reg1<9>>
Sources are:
Output signal of OBUF instance <we/t_9_OBUF>
Output signal of FDRE instance <slv_reg1_9>

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signa
<slv_reg1<13>>
Sources are:
Output signal of OBUF instance <we/t_13_OBUF>
Output signal of FDRE instance <slv_reg1_13>

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signa
<slv_reg1<21>>
Sources are:
Output signal of OBUF instance <we/t_21_OBUF>
Output signal of FDRE instance <slv_reg1_21>

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signa
<slv_reg1<27>>
Sources are:
Output signal of OBUF instance <we/t_27_OBUF>
Output signal of FDRE instance <slv_reg1_27>
----------------for all 0 to 31----------------------------
/gary





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  #8 (permalink)  
Old 07-06-2006, 04:55 AM
MM
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

Gary,

It seems you are thinking as if you were writing software. VHDL is a
hardware description language. You need to understand what hardware you are
trying to create. You have a separate write and read processes, which
essentially describe behaviour of a bunch (because you have more than a
single bit) of D flip-flops. The write process describes what is applied to
the D input and the read process what happens to the Q output. Thus, when
you see slv_reg in the write process on the left side of the assignment it
represents the D-input of the flip-flop, while when you see it on the right
side in the read process it represents the Q output of the same flip-flop,
i.e. stored content of the register.

/Mikhail







"gary" <[email protected]> wrote in message
news:[email protected] ...
> >Gary,
> >
> >h doesn't have a source in your code. You need to add something like

> this:
> >h <= slv_reg0;
> >Or just use slv_reg0 instead of h as input to your inverter and in the

> read
> >process.
> >
> >/Mikhail
> >hey,

> In user_ip.vhd file i used the following instantation in user logic
> implementation
> h<=slv_reg0;
> k<=slv_reg1;
> again synthesis is going on well but the same errors what i posted in my
> first message are coming again.
>
> And in the second method i disabled h & k signals directly i assigned
> portmap(slv_reg0,slv_reg1) in following way
> ------------
> component inverter
> port( s : in std_logic_vector(0 to 31);
> t : out std_logic_vector(0 to 31));
> end component;
>
> ---attribute box_type : string;
> --attribute box_type of inverter : component is "black_box";
>
> begin
>
> we: inverter
> port map(slv_reg0,slv_reg1);
> ----------------------------
> while synthesis following errors are generated....
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal <slv_reg1<9>>
> Sources are:
> Output signal of OBUF instance <we/t_9_OBUF>
> Output signal of FDRE instance <slv_reg1_9>
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
> <slv_reg1<13>>
> Sources are:
> Output signal of OBUF instance <we/t_13_OBUF>
> Output signal of FDRE instance <slv_reg1_13>
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
> <slv_reg1<21>>
> Sources are:
> Output signal of OBUF instance <we/t_21_OBUF>
> Output signal of FDRE instance <slv_reg1_21>
>
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
> <slv_reg1<27>>
> Sources are:
> Output signal of OBUF instance <we/t_27_OBUF>
> Output signal of FDRE instance <slv_reg1_27>
> ----------------for all 0 to 31----------------------------
> /gary
>
>
>
>
>



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  #9 (permalink)  
Old 07-09-2006, 12:02 AM
gary
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

>Gary,
>
>It seems you are thinking as if you were writing software. VHDL is a
>hardware description language. You need to understand what hardware yo

are
>trying to create. You have a separate write and read processes, which
>essentially describe behaviour of a bunch (because you have more than a
>single bit) of D flip-flops. The write process describes what is applie

to
>the D input and the read process what happens to the Q output. Thus

when
>you see slv_reg in the write process on the left side of the assignmen

it
>represents the D-input of the flip-flop, while when you see it on th

right
>side in the read process it represents the Q output of the sam

flip-flop,
>i.e. stored content of the register.
>
>/Mikhail
>
>
>
>
>
>
>
>"gary" <[email protected]> wrote in message
>news:[email protected] m...
>> >Gary,
>> >
>> >h doesn't have a source in your code. You need to add something like

>> this:
>> >h <= slv_reg0;
>> >Or just use slv_reg0 instead of h as input to your inverter and i

the
>> read
>> >process.
>> >
>> >/Mikhail
>> >hey,

>> In user_ip.vhd file i used the following instantation in use

logic
>> implementation
>> h<=slv_reg0;
>> k<=slv_reg1;
>> again synthesis is going on well but the same errors what i posted i

my
>> first message are coming again.
>>
>> And in the second method i disabled h & k signals directly i assigned
>> portmap(slv_reg0,slv_reg1) in following way
>> ------------
>> component inverter
>> port( s : in std_logic_vector(0 to 31);
>> t : out std_logic_vector(0 to 31));
>> end component;
>>
>> ---attribute box_type : string;
>> --attribute box_type of inverter : component is "black_box";
>>
>> begin
>>
>> we: inverter
>> port map(slv_reg0,slv_reg1);
>> ----------------------------
>> while synthesis following errors are generated....
>>
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signa

<slv_reg1<9>>
>> Sources are:
>> Output signal of OBUF instance <we/t_9_OBUF>
>> Output signal of FDRE instance <slv_reg1_9>
>>
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
>> <slv_reg1<13>>
>> Sources are:
>> Output signal of OBUF instance <we/t_13_OBUF>
>> Output signal of FDRE instance <slv_reg1_13>
>>
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
>> <slv_reg1<21>>
>> Sources are:
>> Output signal of OBUF instance <we/t_21_OBUF>
>> Output signal of FDRE instance <slv_reg1_21>
>>
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
>> <slv_reg1<27>>
>> Sources are:
>> Output signal of OBUF instance <we/t_27_OBUF>
>> Output signal of FDRE instance <slv_reg1_27>
>> ----------------for all 0 to 31----------------------------
>> /gary
>>
>>hi mikhael,

sorry iam a beginner, thanks for ur information.In m
user_ip.vhd there are 2 process one for read & another for write, now
want to access my inverter i.e one i/p & one o/p. so i have to write lik
this (h<=slv_reg0 in write process and (k<=slv_reg1in read proces
because iam intended to connect the h to my i/p(s) of inverter and k t
o/p(t) of my inverter.
Can u tell me is this right?

If this is right when i synthesized my code like this following warnin
msg is appearing:
WARNING:Xst:646 - Signal <k> is assigned but never used.
And while implementing same errors as before are appearing.


Before in my user_ip.vhd i used to write my logic (inverter) and when
used to download it on my board and see it on the hyper terminal it work
fine. But when the same logic is added like a (ip core)i.e componen
instantiation, i stucked at the above problems.

So can you guide me in this task.

thanks
gary

>>
>>
>>

>
>
>



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  #10 (permalink)  
Old 07-10-2006, 04:59 PM
MM
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

"gary" <[email protected]> wrote in message
news:[email protected]
> In my
> user_ip.vhd there are 2 process one for read & another for write, now i
> want to access my inverter i.e one i/p & one o/p. so i have to write like
> this (h<=slv_reg0 in write process and (k<=slv_reg1in read process
> because iam intended to connect the h to my i/p(s) of inverter and k to
> o/p(t) of my inverter.
> Can u tell me is this right?


No, it's not. See below corrected write and read processes and assignement
for h.

================================================== ====
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_select is
when "100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

h <= slv_reg0;

-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select,h,k) is
begin

case slv_reg_read_select is
when "100" => slv_ip2bus_data <= h;
when "010" => slv_ip2bus_data <= k;
when others => slv_ip2bus_data <= (others => '0');
end case;

end process SLAVE_REG_READ_PROC;

================================================== ====

/Mikhail


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  #11 (permalink)  
Old 07-11-2006, 10:50 PM
gary
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

hi,
I did it in the same way what you have told, synthesis is going wel
but while implementing design i stucked up at following errors:

ERROR:NgdBuild:809 - output pad net 'k<9>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<27>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<9>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<9>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<21>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<25>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<26>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<20>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<21>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<21>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<8>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<8>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<26>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<26>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<7>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<7>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<19>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<20>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<20>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<18>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<25>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<25>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<24>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<19>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<19>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<23>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<22>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<22>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<24>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<24>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<11>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<11>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<18>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<18>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<22>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<16>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<16>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<23>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<23>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<6>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<6>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<10>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<10>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<15>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<15>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<17>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<17>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<5>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<5>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<17>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<7>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<14>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<14>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<4>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<4>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<11>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<6>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<13>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<13>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<10>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<5>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<16>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<4>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<8>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<15>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<3>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<12>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<12>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<0>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<2>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<2>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<2>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<13>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<3>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<3>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<14>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<1>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<1>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<1>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<31>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'k<12>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<31>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<31>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<30>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<30>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<30>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<0>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<0>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<29>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<29>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<29>' is driving non-buffer
ERROR:NgdBuild:809 - output pad net 'k<28>' has an illegal load:
ERROR:NgdBuild:455 - logical net 'slv_reg0<28>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<28>' is driving non-buffer
ERROR:NgdBuild:455 - logical net 'slv_reg0<27>' has multiple driver(s):
ERROR:NgdBuild:924 - input pad net 'slv_reg0<27>' is driving non-buffer
ERROR: NGDBUILD failed

shall i add any user ports in my design? as of i know user ports are
necessary when iam accessing any ports outside the FPGA.
But iam just instantiating the component in my ip, so its a internal
logic.
can you suggest me?
/gary
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  #12 (permalink)  
Old 07-12-2006, 12:11 AM
MM
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

"gary" <[email protected]> wrote in message
news:[email protected] ...
> hi,
> I did it in the same way what you have told, synthesis is going well
> but while implementing design i stucked up at following errors:
>
> ERROR:NgdBuild:455 - logical net 'slv_reg0<21>' has multiple driver(s):


The multiple driver errors seem to say that you still have wrong assignments
in your code, i.e. you have slv_reg0 on the left side of the equation in
more than one place...

I am not sure about other errors... Try to clean this one first...

/Mikhail



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  #13 (permalink)  
Old 07-27-2006, 09:51 PM
gary
Guest
 
Posts: n/a
Default Re: component instantiation ISE7.1

>
>hi mikhail,

my problem is solved, itz not the problem with my code. Th
componet which iam adding (i.e inverter.vhd) synthesize this file befor
adding to user_logic.vhd file,so that it will generate edif or ngc file
known as netlist files,that can be used in synthesis. After doing thi
right click on the inverter.vhd file and click the option 'move to surce
add it to ur core.
Then it works fine!

regards
gary


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