FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-02-2007, 02:44 AM
Guest
 
Posts: n/a
Default code hang after loading through gdb

Hi,

I'm trying to do a design with dual ppc on an ml410 board with virtex
4. I first followed an example given on xilinx website and everything
seems to be ok. But after I add only one more uartlite (there is
already one in the original design), when I load the code through gdb,
the code hang there and don't stop at the breakpoint at the beginning
of the main function. What could possibly cause the code hang? Since I
didn't touch the software, it has to be hardware problem. I checked
the mhs file and made sure the second uart has same parameter as the
first one. I'm a newbie in using FPGA and don't know what else I
should check. Could anybody give me some direction what I should try?
Thanks.

Reply With Quote
  #2 (permalink)  
Old 11-02-2007, 02:11 PM
morphiend
Guest
 
Posts: n/a
Default Re: code hang after loading through gdb

On Nov 1, 9:44 pm, [email protected] wrote:
> Hi,
>
> I'm trying to do a design with dual ppc on an ml410 board with virtex
> 4. I first followed an example given on xilinx website and everything
> seems to be ok. But after I add only one more uartlite (there is
> already one in the original design), when I load the code through gdb,
> the code hang there and don't stop at the breakpoint at the beginning
> of the main function. What could possibly cause the code hang? Since I
> didn't touch the software, it has to be hardware problem. I checked
> the mhs file and made sure the second uart has same parameter as the
> first one. I'm a newbie in using FPGA and don't know what else I
> should check. Could anybody give me some direction what I should try?
> Thanks.


Try accessing memory from XMD:
mrd <address> <# of 32bit words>
mwr <address> <value> <# of 32bit word repetitions>

Also, you can perform a "sanity" check on the PPC by using 'rrd' to
read all the standard registers. If the same value is "smeared" over
all the registers, besides the PC which will always have the lowest 2
bits be 0, then it usually means that the accesses timed out.

I've seen issues with memory not being accessible and that causes the
situation you are describing.

-- Mike

Reply With Quote
  #3 (permalink)  
Old 11-03-2007, 03:34 AM
Guest
 
Posts: n/a
Default Re: code hang after loading through gdb

Mike,

Thanks for the help. I checked the register values. They are correct.
Also, I tried several memory addresses and they are accessible. After
trying to reload several times, I found that sometimes, one processor
stopped at the beginning as it should be, but the other processor
still failed to do so. Now I'm really lost.

--Cathy

Reply With Quote
  #4 (permalink)  
Old 11-06-2007, 12:29 AM
Guest
 
Posts: n/a
Default Re: code hang after loading through gdb

I found the reason now. In my case, I have several software
applications. When I downloaded the bitstream, sometimes pc register
doesn't contain correct value. Using GDB to download the elf file of
the application I want to run doesn't correct the pc register value
and hence the code hang. But downloading the elf file through xmd
shell can solve the problem.

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Loading Data from Prom Marco T. FPGA 1 01-20-2006 10:01 AM
simulating code loading in memory and jumping to memory sjulhes FPGA 7 11-28-2005 08:02 AM
Internal Loading in Spartan3 motty FPGA 0 10-21-2005 07:33 PM
intermittent sysACE hang on ML310 Bo FPGA 0 03-04-2005 02:12 PM
ChipScope Pro Loading Memory Vivek Joshi FPGA 2 08-04-2004 11:12 PM


All times are GMT +1. The time now is 04:29 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved