FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-10-2006, 06:34 PM
Posts: n/a
Default code

Dear all

First thanks for all give me help


How check independence between row and column in low parity check

What is the advantage of use all one code word in codes?

What is the advantage of Richardson method encoding of LDPC (other than
low complexity?

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
Help with Verilog code flow + Code posted. dash82 Verilog 3 11-30-2007 10:13 PM
Code rsk Verilog 1 05-25-2007 08:47 AM
Looking for 64 bit IEEE802.3 Verilog code or tips for code Vik FPGA 2 12-28-2005 07:53 PM
mux code Ralf Hildebrandt Verilog 4 09-06-2004 05:20 PM
Verilog Netlest Reader Code, ATPG Code Robert Posey Verilog 0 11-19-2003 11:41 PM

All times are GMT +1. The time now is 02:42 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved