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Old 04-19-2006, 02:42 PM
bjzhangwn
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Default clock mux in spartan2e fpga

As I know ,in spartan 2e fpga ,There is no bufgmux,and I want to use
clock mux in the design,can some give me some advice.If I can use a
general mux to mux the two input clock and make the output clock use
the global routing resource?

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Old 04-20-2006, 12:31 AM
JustJohn
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Default Re: clock mux in spartan2e fpga


bjzhangwn wrote:
> As I know ,in spartan 2e fpga ,There is no bufgmux,and I want to use
> clock mux in the design,can some give me some advice.If I can use a
> general mux to mux the two input clock and make the output clock use
> the global routing resource?


This is the second time I can refer someone to Peter's nice article,
"Six Easy Pieces":
Search the Xilinx website, when you find it, look at the sixth piece.

Here's a code snippet:
Clk_A_Proc: process( Clk_A )
begin
if FALLING_EDGE( Clk_A ) then
Use_Clk_A <= not Select_Clk_B
and not Use_Clk_B;
end if;
end process;
Clk_B_Proc: process( Clk_B )
if FALLING_EDGE( Clk_B ) then
Use_Clk_B <= Select_Clk_B
and not Use_Clk_A;
end if;
end process;
Clock <= ( Clk_A and Use_Clk_A )
or ( Clk_B and Use_Clk_B );

Plug this into a design, set the device to an S3E, and the tools do
what you expect. Be careful of the final routing though...if the
routing of either of the Use_Clk_X signals exceeds half a clock period,
you could generate a glitch when switching.

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Old 04-20-2006, 02:54 PM
bjzhangwn
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Default Re: clock mux in spartan2e fpga

Thansks,I want to know what speed the Clock you list above can reach?
50Mhz?I care the sklew when routing!

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  #4 (permalink)  
Old 04-20-2006, 10:15 PM
Peter Alfke
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Default Re: clock mux in spartan2e fpga

You should be able to run 200 MHz, but make sure that the clock
multiplexer is confined to a small area. And then use Global Clock
lines...
Peter Alfke

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Old 04-20-2006, 10:19 PM
JustJohn
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Default Re: clock mux in spartan2e fpga


bjzhangwn wrote:
> Thansks,I want to know what speed the Clock you list above can reach?
> 50Mhz?I care the sklew when routing!


50MHz is easy...it has a half period of 10ns, and I think it's very
hard to get a net delay differential that large in today's parts. I
said be careful about the delay on "Use_Clk_x" before, I meant the
difference in delay between Use_Clk_x and Clk_x at the FF and at the
LUT that does the multiplexing. Take a good close look at the circuit,
understand it, I can't give you everything.

That said, you may want to implement it by instantiating the FF's and
the LUT that does the multiplexing, and then applying LOCs or RLOCs to
them, instead of inferring the devices as in the code snippet I gave.
That way, you can be sure the FFs are close to the LUT. Finally, to be
absolutely sure, you can verify with a post route back-annotated timing
simulation. But this is probably overkill for 50MHz. I'll let you tell
me what speed clock _you_ can reach.

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  #6 (permalink)  
Old 04-20-2006, 10:31 PM
JustJohn
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Posts: n/a
Default Re: clock mux in spartan2e fpga


bjzhangwn wrote:
> Thansks,I want to know what speed the Clock you list above can reach?
> 50Mhz?I care the sklew when routing!


50MHz is easy...it has a half period of 10ns, and I think it's very
hard to get a net delay differential that large in today's parts. I
said be careful about the delay on "Use_Clk_x" before, I meant the
difference in delay between Use_Clk_x and Clk_x at the FF and at the
LUT that does the multiplexing. Take a good close look at the circuit,
understand it, I can't give you everything.

That said, you may want to implement it by instantiating the FF's and
the LUT that does the multiplexing, and then applying LOCs or RLOCs to
them, instead of inferring the devices as in the code snippet I gave.
That way, you can be sure the FFs are close to the LUT. Finally, to be
absolutely sure, you can verify with a post route back-annotated timing
simulation. But this is probably overkill for 50MHz. I'll let you tell
me what speed clock _you_ can reach.

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