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  #1 (permalink)  
Old 04-25-2006, 05:33 PM
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Default clock multiplication

Hi there,

I have a low frequency variable clock frequency (for vari-speed audio
tasks) in the range of 39 KHz to 50 KHz.

Is it easy within an FPGA to implement a 32 times clock multiplier?

Would the circuit be a combination of PLL's?

Any advice/help appreciated!

Thanks, Bob.

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  #2 (permalink)  
Old 04-25-2006, 05:56 PM
Rene Tschaggelar
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Default Re: clock multiplication

[email protected] wrote:

> Hi there,
>
> I have a low frequency variable clock frequency (for vari-speed audio
> tasks) in the range of 39 KHz to 50 KHz.
>
> Is it easy within an FPGA to implement a 32 times clock multiplier?
>
> Would the circuit be a combination of PLL's?
>
> Any advice/help appreciated!


These frequencies are a bit on the low side.
Yes, it may possibly be done with an FPGA, after
dividing the clock down. A normal PLL may be
the better solution though.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
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Old 04-25-2006, 07:02 PM
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Default Re: clock multiplication

Thank you for your response.

Could you detail how a PLL can be used in this instance?

How can I set the multiplication rate at 32?

Would it be able to deal with rapid changes in the input clock?

Thanks, Bob

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  #4 (permalink)  
Old 04-25-2006, 07:17 PM
unfrostedpoptart
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Default Re: clock multiplication


[email protected] wrote:
> Thank you for your response.
>
> Could you detail how a PLL can be used in this instance?


Which FPGA? What company? You need to read about PLLs (or DCMs in
Xilinx).

>
> How can I set the multiplication rate at 32?


Depends on the PLL.
>
> Would it be able to deal with rapid changes in the input clock?


How rapid? How quickly does it need to settle?

Anyway, your input clock is probably way to low frequency to work with
the PLLs/DCMs in FPGAs. They are set up for multi-megaHertz clock
rates. You will likely have to design an outboard PLL (4046?).

David

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  #5 (permalink)  
Old 04-25-2006, 07:39 PM
Rene Tschaggelar
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Default Re: clock multiplication

[email protected] wrote:

> Thank you for your response.
>
> Could you detail how a PLL can be used in this instance?
>
> How can I set the multiplication rate at 32?
>
> Would it be able to deal with rapid changes in the input clock?


As said, forget the FPGA. Take a 4046. Then take
a VCO, such as a LTC6900 resistor set oscillator
and add a div32 divider in the form of 5 Flipflops
or a presetable counter.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
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  #6 (permalink)  
Old 04-25-2006, 08:36 PM
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Default Re: clock multiplication

Thank you all very much!
Please forgive my inexperience!

All the best.

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  #7 (permalink)  
Old 04-26-2006, 12:36 AM
Peter Alfke
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Default Re: clock multiplication

Your design would be much simpler if you had an input clock that varies
between 1.3 and 1.6 MHz. You could then easily generate the 32-times
lower clock frequency with a 5-bit counter.
In your case, you have to build a feedback (or servo) system, that
multiplies the frequency in an indirect way: it adjusts a variable high
frequency (1.2...1.6 MHz Voltage-Controlled Oscillator). This high
frequency is divided by 32 in a 5-bit binary counter, and the output of
this counter is compared (in a phase/frequency detector) against your
incoming 39 to 50 kHz clock. Any frequency or phase difference
generates a control signal that, appopriately filtered, changes the VCO
frequency in the right direction.
A long time constant in the Low-pass filter gives you a very stable
frequency, but slows down the response to any frequency changes of your
incoming clock. A higher cut-off frequency in the Low-pass fiter gives
you less stability, but better agility.
There are many textbooks that describe PLL (Phase-Locked Loop) design.
Any FPGA can implement the counter and also the phase/frequency
detector, but not the VCO.
Peter Alfke, Xilinx Applications

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  #8 (permalink)  
Old 04-26-2006, 12:51 AM
John_H
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Default Re: clock multiplication

<[email protected]> wrote in message
news:[email protected] ups.com...
> Hi there,
>
> I have a low frequency variable clock frequency (for vari-speed audio
> tasks) in the range of 39 KHz to 50 KHz.
>
> Is it easy within an FPGA to implement a 32 times clock multiplier?
>
> Would the circuit be a combination of PLL's?
>
> Any advice/help appreciated!
>
> Thanks, Bob.


Say, could you *generate* the 39kHz or 50 Khz clock with the FPGA? If you
use a fixed 50 MHz system clock (easy in today's FPGAs) you could get a
jitter-free output clock with better than 0.1% frequency accuracy over your
range of interest.

If you can tolerate a little jitter (which I would expect is undesirable for
audio) then a digital phase locked loop could slave a clock generated by the
FPGA back to your reference clock.


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