FPGA Central

hey guys...

can u please tell me a method to reduce the clock frequency of the FPGA
using counters

puneet

Use a DCM(xilinx) or PLL (altera),
or keep the clock frequency the same and use clock enables to run this
logic at a lower rate,
or use a counter to reduce the clock frequency.

What are you trying to do?


[email protected] wrote:
> hey guys...
>
> can u please tell me a method to reduce the clock frequency of the FPGA
> using counters
>
> puneet

"""Andrew FPGA пи�ал(а):
"""
> Use a DCM(xilinx) or PLL (altera),
> or keep the clock frequency the same and use clock enables to run this
> logic at a lower rate,
> or use a counter to reduce the clock frequency.
>

Example (in Verilog):
Generate 8.192 (2.048 * 4) MHz from 19.44 MHz workin on 155.52 (19.44 *
8) MHz
This metod generete parazitic jitter.

//Ìîäóëü ôîðìèðóåò èç 155.52 ÌÃö 8.192 ÌÃö
//Äëÿ ýòîãî Ã*åîáõîäèìî âûäÃ*òü 126 ðÃ*ç 10
ïåðèîäîâ è 130 ðÃ*ç 9 ïåðèîäîâ
//4 ëèøÃ*èõ 9 ïåðèîäîâ âûäÃ*åì Ã*Ã* 1-é, 64-é,
128-é è 193-é ðÃ*çû
module divide_clk (RESET, iCLK, oCLK);
input RESET;
input iCLK;


output oCLK; reg oCLK;


reg [7:0] aCOUNT; //Ñ÷åò÷èê
reg [4:0] bCOUNT; //Ñ÷åò÷èê èÃ*òåðâÃ*ëÃ* 9 èëè
10 CLK


always @(posedge iCLK) begin
if (!RESET) begin
oCLK = 0;
aCOUNT = 0;
bCOUNT = 0;
end //if
else begin
if (aCOUNT <= 63 || (aCOUNT >= 128 && aCOUNT <= 191))
begin
if (aCOUNT == 0 || aCOUNT == 128 || aCOUNT[0]
== 1) begin
if (bCOUNT < 17) begin
if (bCOUNT == 8) oCLK = 1;
bCOUNT = bCOUNT + 1;
end
else begin
oCLK = 0;
bCOUNT = 0;
aCOUNT = aCOUNT + 1;
end
end //if
else if (aCOUNT[0] == 0) begin
if (bCOUNT < 19) begin
if (bCOUNT == 9) oCLK = 1;
bCOUNT = bCOUNT + 1;
end
else begin
oCLK = 0;
bCOUNT = 0;
aCOUNT = aCOUNT + 1;
end
end //else if
end //if
else begin
if (aCOUNT[0] == 1) begin
if (bCOUNT < 19) begin
if (bCOUNT == 9) oCLK = 1;
bCOUNT = bCOUNT + 1;
end
else begin
oCLK = 0;
bCOUNT = 0;
aCOUNT = aCOUNT + 1;
end
end //if
else begin
if (bCOUNT < 17) begin
if (bCOUNT == 8) oCLK = 1;
bCOUNT = bCOUNT + 1;
end
else begin
oCLK = 0;
bCOUNT = 0;
aCOUNT = aCOUNT + 1;
end
end //else
end //else
end //else
end //always


endmodule //divide_clk