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Old 06-19-2005, 10:13 AM
Ibrahim Magdy
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Default clock domain : DDR read enable


I am doing a DDR-controller, using a delayed version of the Data strobe to capture the data, however my main problem lies with the clock-enable signal, it comes from another clock domain and it has to be delayed CAS latency, my problem is it violates setup and hold time each time my design speed differs, is there anyway to avoid this?
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