FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 07-03-2003, 09:19 AM
Stifler
Guest
 
Posts: n/a
Default check one two check check

check check one twoo
Reply With Quote
  #2 (permalink)  
Old 07-03-2003, 04:31 PM
Chris Carlen
Guest
 
Posts: n/a
Default Re: check one two check check

Stifler wrote:
> check check one twoo



You're supposed to say that into a microphone.

Here it goes like this: "this is a test, please ignore."


--
__________________________________________________ _____________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected] -- NOTE: Remove "BOGUS" from email address to reply.

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Check This Out!!! [email protected] Verilog 1 01-16-2008 04:27 PM
bidirectional bus sanity check bmarchio Verilog 7 07-07-2005 05:38 AM
check it please dolly Verilog 2 11-02-2004 08:41 PM
Connectivity check Walter Encinas Verilog 0 07-18-2003 07:01 PM


All times are GMT +1. The time now is 04:25 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved