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  #1 (permalink)  
Old 10-23-2007, 06:44 AM
Guest
 
Posts: n/a
Default Changing refresh rate for DRAM while in operation?

Hi,

I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera
DE2 board. I've gotten the hardware interface squared away (thanks
everyone for your help!).

Now it's the tricky stuff. Any one have an idea how I can change the
refresh rate while the RAM is in operation?

I have the DRAM interface built using the SOPC builder that comes with
Quartus II using the NIOS II system.

I know you can change the refresh rate during the build but I need a
way to change the refresh rate during operation. The only thing I can
think of is maybe change the clock speed? I have it running off a
50Mhz clock....

Thanks,
Eric

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  #2 (permalink)  
Old 10-23-2007, 12:44 PM
KJ
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?


<[email protected]> wrote in message
news:[email protected] oups.com...
> Hi,
>
> I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera
> DE2 board. I've gotten the hardware interface squared away (thanks
> everyone for your help!).
>
> Now it's the tricky stuff. Any one have an idea how I can change the
> refresh rate while the RAM is in operation?
>

The most obvious question would be 'Why?'

> I have the DRAM interface built using the SOPC builder that comes with
> Quartus II using the NIOS II system.
>

That will limit your options (as would probably most other vendor IP DRAM
controllers).

> I know you can change the refresh rate during the build but I need a
> way to change the refresh rate during operation. The only thing I can
> think of is maybe change the clock speed? I have it running off a
> 50Mhz clock....
>

A simpler way would be to simply have a DRAM controller that has an explicit
'Refresh Request' input that would cause the controller to perform a
refresh. Then connect that input up to any programmable timer or other
logic that you would like to use. Changing the clock rate would be far down
on my list of ways to accomplish your goal....but again, it begs the
original question about why you would want to change the refresh rate
dynamically at all.

KJ


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  #3 (permalink)  
Old 10-23-2007, 01:36 PM
David Spencer
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

> Now it's the tricky stuff. Any one have an idea how I can change the
> refresh rate while the RAM is in operation?


Why?


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  #4 (permalink)  
Old 10-23-2007, 06:03 PM
Jim Stewart
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

KJ wrote:
> <[email protected]> wrote in message
> news:[email protected] oups.com...
>> Hi,
>>
>> I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera
>> DE2 board. I've gotten the hardware interface squared away (thanks
>> everyone for your help!).
>>
>> Now it's the tricky stuff. Any one have an idea how I can change the
>> refresh rate while the RAM is in operation?
>>

> The most obvious question would be 'Why?'
>
>> I have the DRAM interface built using the SOPC builder that comes with
>> Quartus II using the NIOS II system.
>>

> That will limit your options (as would probably most other vendor IP DRAM
> controllers).
>
>> I know you can change the refresh rate during the build but I need a
>> way to change the refresh rate during operation. The only thing I can
>> think of is maybe change the clock speed? I have it running off a
>> 50Mhz clock....
>>

> A simpler way would be to simply have a DRAM controller that has an explicit
> 'Refresh Request' input that would cause the controller to perform a
> refresh. Then connect that input up to any programmable timer or other
> logic that you would like to use. Changing the clock rate would be far down
> on my list of ways to accomplish your goal....but again, it begs the
> original question about why you would want to change the refresh rate
> dynamically at all.


Assuming he has a good reason to change it,
the safest thing to do would be to call a
routine in flash to change it.


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  #5 (permalink)  
Old 10-23-2007, 10:04 PM
CBFalconer
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

[email protected] wrote:
>
> I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an
> Altera DE2 board. I've gotten the hardware interface squared away
> (thanks everyone for your help!).
>
> Now it's the tricky stuff. Any one have an idea how I can change
> the refresh rate while the RAM is in operation?
>
> I have the DRAM interface built using the SOPC builder that comes
> with Quartus II using the NIOS II system.
>
> I know you can change the refresh rate during the build but I need
> a way to change the refresh rate during operation. The only thing
> I can think of is maybe change the clock speed? I have it running
> off a 50Mhz clock....


Since the only purpose of the refresh circuitry is to avoid the
memory dropping bits, it should already be running at the slowest
possible rate, and speed reduction will be harmful, while speed
increase will do no good. So this is not a good idea.

What are you trying to do?

--
Chuck F (cbfalconer at maineline dot net)
Available for consulting/temporary embedded and systems.
<http://cbfalconer.home.att.net>



--
Posted via a free Usenet account from http://www.teranews.com

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  #6 (permalink)  
Old 10-24-2007, 12:09 AM
Guest
 
Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

>Since the only purpose of the refresh circuitry is to avoid the
>memory dropping bits, it should already be running at the slowest
>possible rate, and speed reduction will be harmful, while speed
>increase will do no good. So this is not a good idea.
>
>What are you trying to do?


Although it's not expressed in DRAM specs and you wouldn't want to
rely on it, the effect of reducing refresh rate is to increase the
access time. I'm not up-to-date with DRAM technology, but my
experience with devices 30 years ago was that you could turn off
refresh (and all other access) for 10s or more without losing the
contents, provided you weren't pushing the device to its access time
limits.

So, it's not impossible that reducing refresh rate would have a use
(albeit outside the published device spec). But, as you suggest, it
would help if he would just tell us what he's trying to do.

Mike
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  #7 (permalink)  
Old 10-24-2007, 01:27 AM
David Spencer
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?


<[email protected]> wrote in message
news:[email protected]
>
> Although it's not expressed in DRAM specs and you wouldn't want to
> rely on it, the effect of reducing refresh rate is to increase the
> access time. I'm not up-to-date with DRAM technology, but my
> experience with devices 30 years ago was that you could turn off
> refresh (and all other access) for 10s or more without losing the
> contents, provided you weren't pushing the device to its access time
> limits.
>
> So, it's not impossible that reducing refresh rate would have a use
> (albeit outside the published device spec). But, as you suggest, it
> would help if he would just tell us what he's trying to do.
>
> Mike


Although that may well be the case for asynchronous DRAMs (because the
reduced charge in the memory cell capacitor would mean that the sense
amplifier took longer to register the state), this would not be the case for
SDRAM since this registers the outputs a fixed number of clocks after the
access starts. If the underlying access time increased by too much then the
data would just be wrong.


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  #8 (permalink)  
Old 10-24-2007, 06:50 AM
Peter Alfke
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

On Oct 23, 5:27 pm, "David Spencer" <[email protected]> wrote:
> <[email protected]> wrote in message
>
> news:[email protected]
>
>
>
> > Although it's not expressed in DRAM specs and you wouldn't want to
> > rely on it, the effect of reducing refresh rate is to increase the
> > access time. I'm not up-to-date with DRAM technology, but my
> > experience with devices 30 years ago was that you could turn off
> > refresh (and all other access) for 10s or more without losing the
> > contents, provided you weren't pushing the device to its access time
> > limits.

>
> > So, it's not impossible that reducing refresh rate would have a use
> > (albeit outside the published device spec). But, as you suggest, it
> > would help if he would just tell us what he's trying to do.

>
> > Mike

>
> Although that may well be the case for asynchronous DRAMs (because the
> reduced charge in the memory cell capacitor would mean that the sense
> amplifier took longer to register the state), this would not be the case for
> SDRAM since this registers the outputs a fixed number of clocks after the
> access starts. If the underlying access time increased by too much then the
> data would just be wrong.


For certain addressing patterns, the refresh can be eliminated
alltogether, when the addressing sequence is such that all (used)
memory cells are naturally being read, and thus refreshed, within the
required time.
Peter Alfke

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  #9 (permalink)  
Old 10-24-2007, 08:15 AM
Antti
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

On 24 Okt., 07:50, Peter Alfke <[email protected]> wrote:
> On Oct 23, 5:27 pm, "David Spencer" <[email protected]> wrote:
>
>
>
>
>
> > <[email protected]> wrote in message

>
> >news:[email protected] .

>
> > > Although it's not expressed in DRAM specs and you wouldn't want to
> > > rely on it, the effect of reducing refresh rate is to increase the
> > > access time. I'm not up-to-date with DRAM technology, but my
> > > experience with devices 30 years ago was that you could turn off
> > > refresh (and all other access) for 10s or more without losing the
> > > contents, provided you weren't pushing the device to its access time
> > > limits.

>
> > > So, it's not impossible that reducing refresh rate would have a use
> > > (albeit outside the published device spec). But, as you suggest, it
> > > would help if he would just tell us what he's trying to do.

>
> > > Mike

>
> > Although that may well be the case for asynchronous DRAMs (because the
> > reduced charge in the memory cell capacitor would mean that the sense
> > amplifier took longer to register the state), this would not be the case for
> > SDRAM since this registers the outputs a fixed number of clocks after the
> > access starts. If the underlying access time increased by too much then the
> > data would just be wrong.

>
> For certain addressing patterns, the refresh can be eliminated
> alltogether, when the addressing sequence is such that all (used)
> memory cells are naturally being read, and thus refreshed, within the
> required time.
> Peter Alfke- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -


Sinclair ZX?
at least some old Z80 homecomputers used refresh by video scan

Antti




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  #10 (permalink)  
Old 10-24-2007, 08:40 AM
Jonathan Bromley
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

On Wed, 24 Oct 2007 07:15:08 -0000,
Antti <[email protected]> wrote:

>> For certain addressing patterns, the refresh can be eliminated
>> alltogether, when the addressing sequence is such that all (used)
>> memory cells are naturally being read, and thus refreshed, within the
>> required time.
>> Peter Alfke- Zitierten Text ausblenden -
>>
>> - Zitierten Text anzeigen -

>
>Sinclair ZX?
>at least some old Z80 homecomputers used refresh by video scan


Yes, and it's a completely ridiculous way to do it. The
added cost of making frequent additional row accesses is
far greater than the cost of the necessary refresh.

A DRAM row is effectively a cache. When you access a row,
you read the whole row into the DRAM's row buffer as a free
side-effect, and can then make very fast column accesses
to anly location in the row. It's preposterous to throw
away that massive free bandwidth just to save yourself
some refresh effort - unless you're trying to design
a $80 home computer/toy in the early 1980s.

In those days, the video buffer was a sufficiently
large fraction of the overall DRAM that it was
reasonable to lay out the video memory so that
every row was automatically visited by the video
scan, giving a refresh cycle every 20ms (16.7ms
in the USA). That was out-of-spec for many DRAMs
of the day (8ms refresh cycle) but in practice it
worked in almost all cases - and the manufacturers
of those computers had a shoddy enough warranty
policy that they weren't going to worry about a
handful of customers complaining about occasional
mysterious memory corruption on a hot day.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #11 (permalink)  
Old 10-24-2007, 10:04 AM
Hal Murray
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?


>For certain addressing patterns, the refresh can be eliminated
>alltogether, when the addressing sequence is such that all (used)
>memory cells are naturally being read, and thus refreshed, within the
>required time.


That happens in a couple of common cases...

Running video refresh out of DRAM
Running DSP code
Running memory tests

I once worked on a memory board that worked better (at least as
measured by memory diagnostics) when the refresh was clipleaded out.
(We had a bug in the arbiter.)

--
These are my opinions, not necessarily my employer's. I hate spam.

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  #12 (permalink)  
Old 10-24-2007, 03:22 PM
Gabor
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

On Oct 24, 5:04 am, [email protected]jc.megapath.net (Hal
Murray) wrote:
> >For certain addressing patterns, the refresh can be eliminated
> >alltogether, when the addressing sequence is such that all (used)
> >memory cells are naturally being read, and thus refreshed, within the
> >required time.

>
> That happens in a couple of common cases...
>
> Running video refresh out of DRAM
> Running DSP code
> Running memory tests
>
> I once worked on a memory board that worked better (at least as
> measured by memory diagnostics) when the refresh was clipleaded out.
> (We had a bug in the arbiter.)
>
> --
> These are my opinions, not necessarily my employer's. I hate spam.



For SDR SDRAMs, the refresh period depends on the density. Highest
density parts need twice the refresh rate (about 7.8 uS vs 15.6 uS).
If you sensed the part size, or used a DIMM or SO-DIMM with a PROM
for configuration, you may want to set up the refresh rate (once)
after the FPGA is running. A full-fledged SDRAM controller could
also set up other parameters based on a configuration PROM. This
is not something that needs to be dynamic for any given system.
You wouldn't swap out DIMMs with the power on. However it can be
more useful than requiring a different configuration load for the
FPGA depending upon the installed memory.

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  #13 (permalink)  
Old 10-24-2007, 07:29 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

Jonathan, why so aggressive?
I was just pointing out that certain applications naturally perform
sufficient refresh operations in their normal addressing sequence. I
can't see why this is "completely ridiculuous"...
Peter Alfke

On Oct 24, 12:40 am, Jonathan Bromley <[email protected]>
wrote:
> On Wed, 24 Oct 2007 07:15:08 -0000,
>
> Antti <[email protected]> wrote:
> >> For certain addressing patterns, the refresh can be eliminated
> >> alltogether, when the addressing sequence is such that all (used)
> >> memory cells are naturally being read, and thus refreshed, within the
> >> required time.
> >> Peter Alfke- Zitierten Text ausblenden -

>
> >> - Zitierten Text anzeigen -

>
> >Sinclair ZX?
> >at least some old Z80 homecomputers used refresh by video scan

>
> Yes, and it's a completely ridiculous way to do it. The
> added cost of making frequent additional row accesses is
> far greater than the cost of the necessary refresh.
>
> A DRAM row is effectively a cache. When you access a row,
> you read the whole row into the DRAM's row buffer as a free
> side-effect, and can then make very fast column accesses
> to anly location in the row. It's preposterous to throw
> away that massive free bandwidth just to save yourself
> some refresh effort - unless you're trying to design
> a $80 home computer/toy in the early 1980s.
>
> In those days, the video buffer was a sufficiently
> large fraction of the overall DRAM that it was
> reasonable to lay out the video memory so that
> every row was automatically visited by the video
> scan, giving a refresh cycle every 20ms (16.7ms
> in the USA). That was out-of-spec for many DRAMs
> of the day (8ms refresh cycle) but in practice it
> worked in almost all cases - and the manufacturers
> of those computers had a shoddy enough warranty
> policy that they weren't going to worry about a
> handful of customers complaining about occasional
> mysterious memory corruption on a hot day.
>
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> [email protected]://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.



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  #14 (permalink)  
Old 10-24-2007, 07:40 PM
Dave Pollum
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Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

On Oct 24, 2:15 am, Antti <[email protected]> wrote:
> On 24 Okt., 07:50, Peter Alfke <[email protected]> wrote:
>
>
>
> > On Oct 23, 5:27 pm, "David Spencer" <[email protected]> wrote:

>
> > > <[email protected]> wrote in message

>
> > >news:[email protected] .

>
> > > > Although it's not expressed in DRAM specs and you wouldn't want to
> > > > rely on it, the effect of reducing refresh rate is to increase the
> > > > access time. I'm not up-to-date with DRAM technology, but my
> > > > experience with devices 30 years ago was that you could turn off
> > > > refresh (and all other access) for 10s or more without losing the
> > > > contents, provided you weren't pushing the device to its access time
> > > > limits.

>
> > > > So, it's not impossible that reducing refresh rate would have a use
> > > > (albeit outside the published device spec). But, as you suggest, it
> > > > would help if he would just tell us what he's trying to do.

>
> > > > Mike

>
> > > Although that may well be the case for asynchronous DRAMs (because the
> > > reduced charge in the memory cell capacitor would mean that the sense
> > > amplifier took longer to register the state), this would not be the case for
> > > SDRAM since this registers the outputs a fixed number of clocks after the
> > > access starts. If the underlying access time increased by too much then the
> > > data would just be wrong.

>
> > For certain addressing patterns, the refresh can be eliminated
> > alltogether, when the addressing sequence is such that all (used)
> > memory cells are naturally being read, and thus refreshed, within the
> > required time.
> > Peter Alfke- Zitierten Text ausblenden -

>
> > - Zitierten Text anzeigen -

>
> Sinclair ZX?
> at least some old Z80 homecomputers used refresh by video scan
>
> Antti


If I recall, the Apple II also refreshed its RAM this way, too.
-Dave Pollum

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  #15 (permalink)  
Old 10-24-2007, 09:40 PM
Jonathan Bromley
Guest
 
Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

On Wed, 24 Oct 2007 11:29:29 -0700, Peter Alfke <[email protected]>
wrote:

>Jonathan, why so aggressive?


Ooh, I can be much more aggressive than that! And it
certainly wasn't directed at you.

>I was just pointing out that certain applications naturally perform
>sufficient refresh operations in their normal addressing sequence. I
>can't see why this is "completely ridiculuous"...


Nor is it; the absurdity comes from bending the addressing
so that only a small part of each row is sequentially accessed,
thereby wasting the massive increase in memory bandwidth that
can be achieved for sequential-access applications by using
the row buffer as a cache. My spleen was being vented at some
designers of old computers (as alluded to by Antti, not you)
who used video scan to access every row of DRAM on each video
field, thereby unnecessarily burning-up memory bandwidth
(which was in short enough supply on such machines) in order
to save the trouble of doing refresh properly...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #16 (permalink)  
Old 10-24-2007, 09:59 PM
Jonathan Bromley
Guest
 
Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

On Wed, 24 Oct 2007 13:06:34 -0800,
glen herrmannsfeldt <[email protected]> wrote:

>Processor speed has increased somewhat faster than DRAM speed.


Indeed so; a fair point. And you could perhaps also argue
that the cost of row access, as a fraction of a data access,
has increased quite dramatically over that time.

>> A DRAM row is effectively a cache. When you access a row,
>> you read the whole row into the DRAM's row buffer as a free
>> side-effect, and can then make very fast column accesses
>> to anly location in the row. It's preposterous to throw
>> away that massive free bandwidth just to save yourself
>> some refresh effort - unless you're trying to design
>> a $80 home computer/toy in the early 1980s.

>
>When RAM cycle time was faster than processor cycle time.


That too is an interesting point. My own experience of
that sort of video controller was that they typically
caused lots of processor stalling while video data
was being fetched, but it may have been different
for other designs.

>If you address it such that sequential characters are
>in different rows then it is refreshed much faster than
>the frame rate.


True, but then you are *really* wasting bandwidth
by doing more row accesses than necessary.

I guess you could, by juggling the use of address bits
sufficiently cunningly, arrange that row accesses by
video scan would *just* provide enough refresh to
satisfy the data sheet spec.

I've seen many different variants on this: block refresh
during frame blanking, for example. They all seemed
pretty unpleasant to me at the time, and still seem so
now - although, of course, no-one needs to do that sort
of dirty trick any more (do they? please?)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #17 (permalink)  
Old 10-24-2007, 10:06 PM
glen herrmannsfeldt
Guest
 
Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

Jonathan Bromley wrote:
(snip)

> Yes, and it's a completely ridiculous way to do it. The
> added cost of making frequent additional row accesses is
> far greater than the cost of the necessary refresh.


Processor speed has increased somewhat faster than DRAM speed.

> A DRAM row is effectively a cache. When you access a row,
> you read the whole row into the DRAM's row buffer as a free
> side-effect, and can then make very fast column accesses
> to anly location in the row. It's preposterous to throw
> away that massive free bandwidth just to save yourself
> some refresh effort - unless you're trying to design
> a $80 home computer/toy in the early 1980s.


When RAM cycle time was faster than processor cycle time.

> In those days, the video buffer was a sufficiently
> large fraction of the overall DRAM that it was
> reasonable to lay out the video memory so that
> every row was automatically visited by the video
> scan, giving a refresh cycle every 20ms (16.7ms
> in the USA). That was out-of-spec for many DRAMs
> of the day (8ms refresh cycle) but in practice it
> worked in almost all cases - and the manufacturers
> of those computers had a shoddy enough warranty
> policy that they weren't going to worry about a
> handful of customers complaining about occasional
> mysterious memory corruption on a hot day.


Any access to the row will refresh the whole row.
If you address it such that sequential characters are
in different rows then it is refreshed much faster than
the frame rate.

-- glen

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  #18 (permalink)  
Old 10-24-2007, 10:39 PM
MitchAlsup
Guest
 
Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

On Oct 23, 4:04 pm, CBFalconer <[email protected]> wrote:
> Since the only purpose of the refresh circuitry is to avoid the
> memory dropping bits, it should already be running at the slowest
> possible rate, and speed reduction will be harmful, while speed
> increase will do no good. So this is not a good idea.


I disagree (softly), having designed several memory controllers, I
always found it easier to just insert a READ DATA command into the
DRAM when a refresh was needed, rather than insert a refresh command.
The timing differences between refresh and a loosly coupled string of
READS is such that one can refresh ahead with READs easier and then be
in a position to absorb a longer string of demand requests by not
using the REFRESH commands. Thus while running at the slowest overall
rate, one can bunch and distribute the refresh mechanics to better
interleave same with the demand memory requests and gain something.

But I will state the overall performance differences are a fraction of
the refresh overhead anyways.

> What are you trying to do?


That is the real question.

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  #19 (permalink)  
Old 10-24-2007, 11:23 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Changing refresh rate for DRAM while in operation?

Jonathan Bromley wrote:
> On Wed, 24 Oct 2007 11:29:29 -0700, Peter Alfke <[email protected]>
> wrote:
>
>
>>Jonathan, why so aggressive?

>
>
> Ooh, I can be much more aggressive than that! And it
> certainly wasn't directed at you.
>
>
>>I was just pointing out that certain applications naturally perform
>>sufficient refresh operations in their normal addressing sequence. I
>>can't see why this is "completely ridiculuous"...

>
>
> Nor is it; the absurdity comes from bending the addressing
> so that only a small part of each row is sequentially accessed,
> thereby wasting the massive increase in memory bandwidth that
> can be achieved for sequential-access applications by using
> the row buffer as a cache. My spleen was being vented at some
> designers of old computers (as alluded to by Antti, not you)
> who used video scan to access every row of DRAM on each video
> field, thereby unnecessarily burning-up memory bandwidth
> (which was in short enough supply on such machines) in order
> to save the trouble of doing refresh properly...


The bandwidth is there for the designer to use how they wish.
It also only actually matters, if that bandwidth is the
bottleneck in the total design.

eg I have done designs using interleaved video access, which removes
flicker, and makes the system appear to be dual-port.
On your yardstick, because the bandwidth is not 100% used, this
is a bad design ?

-jg

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  #20 (permalink)  
Old 10-24-2007, 11:46 PM
Ray Andraka
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Default Re: Changing refresh rate for DRAM while in operation?

Peter Alfke wrote:


>
> For certain addressing patterns, the refresh can be eliminated
> alltogether, when the addressing sequence is such that all (used)
> memory cells are naturally being read, and thus refreshed, within the
> required time.
> Peter Alfke
>


Such as for a video processor. I've done several that used no refresh.
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  #21 (permalink)  
Old 10-24-2007, 11:55 PM
Ray Andraka
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Default Re: Changing refresh rate for DRAM while in operation?

Peter Alfke wrote:

> Jonathan, why so aggressive?
> I was just pointing out that certain applications naturally perform
> sufficient refresh operations in their normal addressing sequence. I
> can't see why this is "completely ridiculuous"...
> Peter Alfke
>
> On Oct 24, 12:40 am, Jonathan Bromley <[email protected]>
> wrote:
>


>>Yes, and it's a completely ridiculous way to do it. The
>>added cost of making frequent additional row accesses is
>>far greater than the cost of the necessary refresh.
>>


>>

And by not having to perform explicit refreshes, the bandwidth is
slightly higher and latency is more predictable. If your application is
one that always addresses all the memory that it uses (no need to
refresh rows you are not using) within the minimum refresh interval,
then this can sometimes be used to simplify the system. There are still
plenty of FPGA applications that, for example, use the DRAM only for a
video frame buffer.
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  #22 (permalink)  
Old 10-25-2007, 06:35 AM
Paul Keinanen
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Default Re: Changing refresh rate for DRAM while in operation?

On Wed, 24 Oct 2007 14:39:16 -0700, MitchAlsup <[email protected]>
wrote:

>On Oct 23, 4:04 pm, CBFalconer <[email protected]> wrote:
>> Since the only purpose of the refresh circuitry is to avoid the
>> memory dropping bits, it should already be running at the slowest
>> possible rate, and speed reduction will be harmful, while speed
>> increase will do no good. So this is not a good idea.



>But I will state the overall performance differences are a fraction of
>the refresh overhead anyways.
>
>> What are you trying to do?

>
>That is the real question.


If the idea is to reduce the refresh overhead on a busy bus, reducing
the relatively slow refresh rate does not make much sense.

However, if the memory content is to be maintained for a long time
without any data access in a battery powered device, it would make
sense to reduce the refresh rate at low ambient temperatures. The high
refresh rates are needed at the top end of the temperature range, but
at lower temperatures, a slower refresh rate would be sufficient,
which reduces the power consumption and increase battery life.
Unfortunately, refresh rate figures are seldom available for lower
temperatures.

Paul

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  #23 (permalink)  
Old 10-25-2007, 09:34 AM
Sean Durkin
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Default Re: Changing refresh rate for DRAM while in operation?

Paul Keinanen wrote:
> However, if the memory content is to be maintained for a long time
> without any data access in a battery powered device, it would make
> sense to reduce the refresh rate at low ambient temperatures. The high
> refresh rates are needed at the top end of the temperature range, but
> at lower temperatures, a slower refresh rate would be sufficient,
> which reduces the power consumption and increase battery life.
> Unfortunately, refresh rate figures are seldom available for lower
> temperatures.

If you were really aiming for long run time on battery power, I suppose
you'd just use DRAM devices specifically made for such an application.

Mobile SDRAM devices often have a temperature compensated self refresh
feature. You just enter a special suspend mode and the device does the
refresh itself, and only as often as required according to the current
temperature. You can also tell it to just refresh a part of the memory
array, in case you don't use it all.

This is usually way better than anything one could do on his/her own.

So, the question still stands: What does the OP really want to do?

cu,
Sean

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Try figuring out what the address is going to be after that...
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  #24 (permalink)  
Old 10-25-2007, 02:46 PM
Andy
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Default Re: Changing refresh rate for DRAM while in operation?

On Oct 24, 1:40 pm, Dave Pollum <[email protected]> wrote:
> On Oct 24, 2:15 am, Antti <[email protected]> wrote:
>
>
>
> > On 24 Okt., 07:50, Peter Alfke <[email protected]> wrote:

>
> > > On Oct 23, 5:27 pm, "David Spencer" <[email protected]> wrote:

>
> > > > <[email protected]> wrote in message

>
> > > >news:[email protected] .

>
> > > > > Although it's not expressed in DRAM specs and you wouldn't want to
> > > > > rely on it, the effect of reducing refresh rate is to increase the
> > > > > access time. I'm not up-to-date with DRAM technology, but my
> > > > > experience with devices 30 years ago was that you could turn off
> > > > > refresh (and all other access) for 10s or more without losing the
> > > > > contents, provided you weren't pushing the device to its access time
> > > > > limits.

>
> > > > > So, it's not impossible that reducing refresh rate would have a use
> > > > > (albeit outside the published device spec). But, as you suggest, it
> > > > > would help if he would just tell us what he's trying to do.

>
> > > > > Mike

>
> > > > Although that may well be the case for asynchronous DRAMs (because the
> > > > reduced charge in the memory cell capacitor would mean that the sense
> > > > amplifier took longer to register the state), this would not be the case for
> > > > SDRAM since this registers the outputs a fixed number of clocks after the
> > > > access starts. If the underlying access time increased by too much then the
> > > > data would just be wrong.

>
> > > For certain addressing patterns, the refresh can be eliminated
> > > alltogether, when the addressing sequence is such that all (used)
> > > memory cells are naturally being read, and thus refreshed, within the
> > > required time.
> > > Peter Alfke- Zitierten Text ausblenden -

>
> > > - Zitierten Text anzeigen -

>
> > Sinclair ZX?
> > at least some old Z80 homecomputers used refresh by video scan

>
> > Antti

>
> If I recall, the Apple II also refreshed its RAM this way, too.
> -Dave Pollum


The TRS-80 Color Computer (Moto 6809 based) refreshed during the
vertical retrace. But there was a bit in the system controller that
could be set to turn it and video access off, while doubling the
processor clock. As long as your Basic code was running, and not
waiting on a keyboard input or other event, the ROM interpreter's RAM
accesses managed to keep the RAM (at least the part of it being used)
refreshed. But if/when the code hit an error (and thus waited for user
response) you could watch the screen go from random pixels to all
white. Once the coding errors were eliminated, it was a reliable way
to double the processing speed when you did not need video.

Ah the good old days... but, I digress.

Andy

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  #25 (permalink)  
Old 10-25-2007, 02:54 PM
CBFalconer
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Default Re: Changing refresh rate for DRAM while in operation?

MitchAlsup wrote:
> CBFalconer <[email protected]> wrote:
>
>> Since the only purpose of the refresh circuitry is to avoid the
>> memory dropping bits, it should already be running at the slowest
>> possible rate, and speed reduction will be harmful, while speed
>> increase will do no good. So this is not a good idea.

>
> I disagree (softly), having designed several memory controllers,
> I always found it easier to just insert a READ DATA command into
> the DRAM when a refresh was needed, rather than insert a refresh
> command. The timing differences between refresh and a loosly
> coupled string of READS is such that one can refresh ahead with
> READs easier and then be in a position to absorb a longer string
> of demand requests by not using the REFRESH commands. Thus while
> running at the slowest overall rate, one can bunch and distribute
> the refresh mechanics to better interleave same with the demand
> memory requests and gain something.
>
> But I will state the overall performance differences are a
> fraction of the refresh overhead anyways.
>
>> What are you trying to do?

>
> That is the real question.


Since the OP seems to have disappeared to wherever OPs go, I
suspect we will never find out.

--
Chuck F (cbfalconer at maineline dot net)
Available for consulting/temporary embedded and systems.
<http://cbfalconer.home.att.net>



--
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