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Old 11-29-2007, 08:10 AM
chesi
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Default Cascaded DCMs with variable phase shift (Xilinx)

Hi all,

I'm using a Spartan-3 XC3S400 with cascaded DCMs.
1st DCM is configured as variable phase shift with 27MHz clock from an
external VCXO in CLKIN. It is fedback (1X) from CLK0 through an IOB
(run out of BUFG). This IOB's output feeds second DCM's CLKIN. First
DCM's CLKFX output is also used for other tasks (multiplied by 4).
2nd DCM simply uses CLK0 and CLKFX (multiplied by 10) outputs with
BUFG for both of them and the proper feedback 1X from CLK0.
Attributes for both DCMs:
FACTORY_JF => X"8080"
STARTUP_WAIT => FALSE

This structure above is instantiated twice, so I use the 4 DCM of my
FPGA. Both instantiations are identical.

The result of this is that one instantiation works perfectly, but the
other one not. This one successes to set most phase-shift values, but
fails just to set negative phase-shifts (PSINCDEC=0) in the range
between 20 and 28 (nr. of pulses of PSCLK while PSEN is high). The
rest of the phase-shifts are achieved OK. When it fails the DCM's lock
and status bits do not indicate any error situation but ALL the clocks
generated within the FPGA from the VCXO start to move their edges of
the clock pulses pretty much (even clocks not generated by DCM).

I reset DCMs as Xilinx advises (waiting the lock of the 1st DCM to
reset the second one). Has any of you experienced some similar
behaviour?

Regards,
CÚsar
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Old 11-29-2007, 03:46 PM
austin
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Default Re: Cascaded DCMs with variable phase shift (Xilinx)

chesi,

I am looking into this now.

My concern is that feeding a phase shifted clock out of one DCM into
another that is set to multiply by ten (10) may not work (I never
simulated that case). Not sure what the second DCM will do while the
input clock is changing phase (it might lose lock).

I am presuming that your problem is not with the second DCM, but with
the first one? It does not perform the negative phase shifts between 20
and 28 counts?

At 27 MHz, that is a 37 ns period, so each count is 27,000/256 =~ 105
ps. Given that there is a finite number of delay taps, I believe the
lower frequency limit is 19 MHz, there should be no reason you are
running out of taps (and the status register would indicate overflow or
underflow, and you would lose lock).

I will discuss this, and post again.

Austin
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Old 11-30-2007, 07:12 AM
chesi
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Default Re: Cascaded DCMs with variable phase shift (Xilinx)

On 29 nov, 16:46, austin <[email protected]> wrote:
> chesi,
> I am looking into this now.
> My concern is that feeding a phase shifted clock out of one DCM into
> another that is set to multiply by ten (10) may not work (I never
> simulated that case). Not sure what the second DCM will do while the
> input clock is changing phase (it might lose lock).
> I am presuming that your problem is not with the second DCM, but with
> the first one? It does not perform the negative phase shifts between 20
> and 28 counts?
> At 27 MHz, that is a 37 ns period, so each count is 27,000/256 =~ 105
> ps. Given that there is a finite number of delay taps, I believe the
> lower frequency limit is 19 MHz, there should be no reason you are
> running out of taps (and the status register would indicate overflow or
> underflow, and you would lose lock).
> I will discuss this, and post again.
> Austin


Hi,
I've discovered something about this. The problem appears only when
the top-left DCM has to carry out variable phase shift. If I avoid
this situation using LOC constraints, everything seems to work ok. By
the moment I have just one board to try. As soon as I can try with
other ones, I'll try to find if this issue has some repetitive nature.

Regards,
CÚsar
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  #4 (permalink)  
Old 11-30-2007, 06:48 PM
austin
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Default Re: Cascaded DCMs with variable phase shift (Xilinx)

OK,

Here is an answer from the experts:

"Hi Austin,

We took a quick look at this don't see any major issues. It looks as if
he is using the inverted lock signal from the first DCM to reset the
second DCM. No problems here.

Not sure why is CLKFB for first DCM is fed through an IOB. External
feedback? Can add noise perhaps?

I don't think he is using the variable PS correctly though. See this link.

http://www.xilinx.com/support/answers/13824.htm

For every PSEN pulse, I believe the user must wait for PSDONE high
before asserting PSEN again. In this case, it seems like he is just
holding PSEN high for a number of PSCLK cycles, expecting to see an
increment for each PSCLK cycle that the signal was held high for. This
may explain why he is seeing failures.

Let me know if you think this is the case."

Austin
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