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Old 04-19-2006, 12:26 AM
Ingenrepons
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Default cannot be synthesized, bad synchronous description

In connection with "Create Timing Constraints" the error ERROR:Xst:827 occurs.

We have the following fragment in our program:

--------------------------------- process (ARMFPGA1, FRAME_VALID, ARMFPGA3) begin if (ARMFPGA1='1' and ARMFPGA1'event) then -- state=1 when rising_edge(ARMFPGA1) state <= '1'; end if; if (FRAME_VALID='0') then state <= '0'; end if; if (ARMFPGA3='1' and ARMFPGA3'event) then state <= '0'; end if; end process; ---------------------------------

The intention is to:
* set state=1 when rising_edge(ARMFPGA1)
* set state=0 when (falling_edge(FRAME_VALID) or rising_edge(ARMFPGA3))

But according to: <http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPagePath=1404 7&[email protected]@@@[email protected]@@@&BV_En gineID=cccgaddhighjkihcefeceihdffhdfjf.0> you can only have one ’event in a process.

Is it then impossible to realize the following wish: ???
* set state=1 when rising_edge(ARMFPGA1)
* set state=0 when (falling_edge(FRAME_VALID) or rising_edge(ARMFPGA3))
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