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Old 12-03-2008, 12:41 AM
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Default CameraLink Deserilization and Module Constraint Files

Hey Guys,

I have used Xilinx XAPP485 to generate a cameralink deserializing
module as the first part in an image processing chain. The problem I
am facing is that I need to create a new top module in order to link
the outputs of the Xilinx module to the start of my image processing
design, and this is causing issues with the Xilinx UCF file.

It designated which pins to map the primary nets, but also forced the
location of two of the edge alignment modules with the RLOC_ORIGIN
constraint. Ont op of this it also generated some clock periods to be
used.

Now I cant use this constraint set because the module it pertains to
is no longer the top, but I also cannot use it on my new top module
(which just wires the two main components up) because the instantiated
modules it refers to do not exist.

Any ideas? Can you specify any constraints for non top modules?

Gints
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Old 12-03-2008, 01:32 PM
Martin Thompson
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Default Re: CameraLink Deserilization and Module Constraint Files

[email protected] writes:

<snip>
> Any ideas? Can you specify any constraints for non top modules?


Hi,

Yes you can - you just need to find out what the things you want to
constrain are called now that they are one-level down. If you open
the NCD in FPGA editor, you should be able to find the things you are
trying to constrain, and the hierarchical pathname they've been given
by the tools. There's probably a /toplevelname/ prepended to them
all.

Cheers,
Martin

--
[email protected]
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
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  #3 (permalink)  
Old 12-03-2008, 08:46 PM
Gabor
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Default Re: CameraLink Deserilization and Module Constraint Files

On Dec 3, 8:32*am, Martin Thompson <[email protected]> wrote:
> [email protected] writes:
>
> <snip>
>
> > Any ideas? Can you specify any constraints for non top modules?

>
> Hi,
>
> Yes you can - you just need to find out what the things you want to
> constrain are called now that they are one-level down. *If you open
> the NCD in FPGA editor, you should be able to find the things you are
> trying to constrain, and the hierarchical pathname they've been given
> by the tools. *There's probably a /toplevelname/ prepended to them
> all.
>
> Cheers,
> Martin
>
> --
> [email protected]
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html


Also note that you can use wildcards in the ucf for net names or
instance names like
NET "*/foobar" LOC = "AB12" ;

Then you can have constraints that don't break if you change instance
names.
Just remember that this can create problems if the expanded wildcard
name
is not unique.

Regards,
Gabor
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Old 12-03-2008, 11:27 PM
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Default Re: CameraLink Deserilization and Module Constraint Files

Thanks guys I was hoping that was the case, seemed logical.

Will check it out now,

Gints-
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