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  #1 (permalink)  
Old 04-21-2006, 04:51 PM
freechip
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Default CAM, TCAM in Stratix


Hi,
I am working on a 10 Gb Ethernet project (deep packet inspection) and nee
to implement CAM in my FPGA. I am using a Stratix GX and I don't think
can use CAM (internal or external) in the stratix GX Dev Board.

Let me know your thoughts about that.

Thanks a lot.
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  #2 (permalink)  
Old 04-21-2006, 05:03 PM
Austin Lesea
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Default Re: CAM, TCAM in Stratix

Freechip,

http://www.xilinx.com/products/desig...ouping/cam.htm

I am not suggesting you switch to Xilinx, but we do have answers.

Austin

freechip wrote:

> Hi,
> I am working on a 10 Gb Ethernet project (deep packet inspection) and need
> to implement CAM in my FPGA. I am using a Stratix GX and I don't think I
> can use CAM (internal or external) in the stratix GX Dev Board.
>
> Let me know your thoughts about that.
>
> Thanks a lot.

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  #3 (permalink)  
Old 04-21-2006, 05:09 PM
John_H
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Default Re: CAM, TCAM in Stratix

"freechip" <[email protected]> wrote in message
news:[email protected]
>
> Hi,
> I am working on a 10 Gb Ethernet project (deep packet inspection) and need
> to implement CAM in my FPGA. I am using a Stratix GX and I don't think I
> can use CAM (internal or external) in the stratix GX Dev Board.
>
> Let me know your thoughts about that.
>
> Thanks a lot.


How big a (Ternary?)CAM do you need?


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  #4 (permalink)  
Old 04-24-2006, 10:47 AM
freechip
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Default Re: CAM, TCAM in Stratix

>"freechip" <[email protected]> wrote in message
>news:[email protected]
>>
>> Hi,
>> I am working on a 10 Gb Ethernet project (deep packet inspection) an

need
>> to implement CAM in my FPGA. I am using a Stratix GX and I don't thin

I
>> can use CAM (internal or external) in the stratix GX Dev Board.
>>
>> Let me know your thoughts about that.
>>
>> Thanks a lot.

>
>How big a (Ternary?)CAM do you need?
>
>


Hi,
I don't yet.
Do you think it is possible with Altera products?
Have a good day.


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  #5 (permalink)  
Old 04-24-2006, 11:43 AM
Guest
 
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Default Re: CAM, TCAM in Stratix

Hi freechip,

yes I think it is possible to build a CAM
around Altera RAM blocks.

How big is the CAM ? After how many clock cycles
do you need a hit ?

Rgds
André

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  #6 (permalink)  
Old 04-24-2006, 12:54 PM
freechip
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Default Re: CAM, TCAM in Stratix

>Hi freechip,
>
>yes I think it is possible to build a CAM
>around Altera RAM blocks.
>
>How big is the CAM ? After how many clock cycles
>do you need a hit ?
>
>Rgds
>Andr=E9
>
>


Hi Andr,
Actually, I am in the research phase and I really don't know how big i
the cam. I just wanted to know, to compare to Xilinx Family, if it wa
poosible to use cam with Altera product. For my project (deep packe
inspection), the use of the cam is necessary.
If you can tell me how can a build a cam around Altera RAM block (and th
max. of the cam without my answers to your questions), I will be ver
pleased.

Thanks.


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  #7 (permalink)  
Old 04-24-2006, 02:13 PM
John_H
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Default Re: CAM, TCAM in Stratix

>>How big a (Ternary?)CAM do you need?
>>
>>

freechip wrote:
>
> Hi,
> I don't yet.
> Do you think it is possible with Altera products?
> Have a good day.


It's possible to build teeny, tiny CAMs. The information Austin pointed
out gives you an idea of what you can accomplish with FPGA resources
that can apply to all FPGAs, not just Xilinx.

If you need a few entries, you might be okay. If you need small
entries, you may be able to do many more.

Read that documentation and you'll get a feel for the limits you're
faced with.

Personally, I'd love a 4kx20 CAM but I know there's no way to do it in
an FPGA>
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  #8 (permalink)  
Old 04-24-2006, 06:54 PM
Mike Treseler
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Default Re: CAM, TCAM in Stratix

John_H wrote:

> It's possible to build teeny, tiny CAMs. The information Austin pointed
> out gives you an idea of what you can accomplish with FPGA resources
> that can apply to all FPGAs, not just Xilinx.
>
> If you need a few entries, you might be okay. If you need small
> entries, you may be able to do many more.


However, if you plan decode 32 bit or 128 bit IP addresses,
an FPGA solution will likely cost just as much and not
work quite as well as a real CAM.

-- Mike Treseler
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  #9 (permalink)  
Old 04-24-2006, 07:31 PM
John_H
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Posts: n/a
Default Re: CAM, TCAM in Stratix

"Mike Treseler" <[email protected]> wrote in message
news:[email protected]
>
> However, if you plan decode 32 bit or 128 bit IP addresses,
> an FPGA solution will likely cost just as much and not
> work quite as well as a real CAM.
>
> -- Mike Treseler


But if each 128-bit IP address only needs 4 slices and the number of IP
addresses is rather limited, the cost can be much better than a real CAM.


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  #10 (permalink)  
Old 04-25-2006, 02:22 PM
freechip
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Default Re: CAM, TCAM in Stratix

Thanks a lot for your answers.
Actually, I can not tell you more about the size of the CAM.
You are talking about the size but did you implement cam in Alter
(Stratix?) because I didn't see it was possible to put cam in Stratix i
Altera's website.
Have a nice day.

Freechip
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  #11 (permalink)  
Old 04-25-2006, 02:39 PM
John_H
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Posts: n/a
Default Re: CAM, TCAM in Stratix

freechip wrote:
> Thanks a lot for your answers.
> Actually, I can not tell you more about the size of the CAM.
> You are talking about the size but did you implement cam in Altera
> (Stratix?) because I didn't see it was possible to put cam in Stratix in
> Altera's website.
> Have a nice day.
>
> Freechip


Right, right. My apologies. I'm just so used to having embedded
LUT-style memories available that I have trouble making the mindset
switch to Altera. In Altera, CAMs suck (except maybe for way back in
the 20K days).

You can still use the embedded memories to build up a CAM in segments
for a small number of entries. Using the 4k memories arranged as
256x16, you could build 16 CAMs in 8-bit segments. 16 CAM entries of
128 bits would take 16 4k RAM blocks and qty 16, 16-wide cascades to
indicate a byte match for all 16 memories for one CAM entry.

So it can be done but with significantly more resources than the 64
slices needed in an SRL or single-port LUT-RAM device.
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