FPGA Central

Hi,all
After synthesis(Synplify Pro), I got how many LUTs I consumed,
How to equally convert it to the number of logic gates? The device is
the Xilinx VirtexE.
Thanks,
Jason

>After synthesis(Synplify Pro), I got how many LUTs I consumed,
>How to equally convert it to the number of logic gates? The device is
>the Xilinx VirtexE.

Quick answer: There isn't any easy way. It depends upon how much
logic your design put in each LUT.

Crazy question... What's the most number of gates that anybody
has ever put into a LUT? Might be a fun hack to try all possible
functions, translate to gates, maybe run some minimization stuff,
and remember the worst case.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
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Hal Murray wrote:

>>After synthesis(Synplify Pro), I got how many LUTs I consumed,
>>How to equally convert it to the number of logic gates? The device is
>>the Xilinx VirtexE.
>
>
> Quick answer: There isn't any easy way. It depends upon how much
> logic your design put in each LUT.
>
> Crazy question... What's the most number of gates that anybody
> has ever put into a LUT? Might be a fun hack to try all possible
> functions, translate to gates, maybe run some minimization stuff,
> and remember the worst case.

No no.. don't even _think_ about that, imagine what the market droids
could do with that information!!
-jg

Many years ago, i tried to come up with the largest number of 2-input NAND
gates that could be hidden in a 4-LUT.
I thing the number was around 20. It involved many XORs which count as four
NANDs.
There must be a scientific answer to this:
What's the function of four variables that irreducibly requires the largest
number of 2NAND functions to implement ?

Peter Alfke

> From: [email protected] (Hal Murray)
> Newsgroups: comp.arch.fpga
> Date: Wed, 21 Apr 2004 00:08:31 -0000
> Subject: Re: calculate the number of logic gate in FPGA
>
>> After synthesis(Synplify Pro), I got how many LUTs I consumed,
>> How to equally convert it to the number of logic gates? The device is
>> the Xilinx VirtexE.
>
> Quick answer: There isn't any easy way. It depends upon how much
> logic your design put in each LUT.
>
> Crazy question... What's the most number of gates that anybody
> has ever put into a LUT? Might be a fun hack to try all possible
> functions, translate to gates, maybe run some minimization stuff,
> and remember the worst case.
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
>

Peter Alfke <[email protected]> wrote in
news:BCAB2347.5F88%[email protected]:

> Many years ago, i tried to come up with the largest number of 2-input
> NAND gates that could be hidden in a 4-LUT.
> I thing the number was around 20. It involved many XORs which count as
> four NANDs.
> There must be a scientific answer to this:
> What's the function of four variables that irreducibly requires the
> largest number of 2NAND functions to implement ?

A 4-input truth-table can be represented by a 16-node hypercube. You can
select 8 nodes of the 16 such that none of these selected nodes are
adjacent. Each of these nodes represents a 4-input minterm and since
they are non-adjacent there is no possibility of combining minterms. A
4-input minterm requires 3 AND gates and some inverters. Then the 8
minterms have to be OR'ed together which requires another 7 OR gates. So
that totals to 8 * 3 + 7 = 31 2-input gates. I don't have any proof that
this is a maximum, but it seems adding more minterms would allow some
combining of minterms and that would reduce the number of gates needed,
as would removing any minterms.

Here's a function derived using this idea:

F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D +
A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D

If you allow some of the outputs of the 2-input AND gates to be shared
across minterms, then you can cut 8 AND gates and get down to 23 2-input
gates.

>
> Peter Alfke
>
>> From: [email protected] (Hal Murray)
>> Newsgroups: comp.arch.fpga
>> Date: Wed, 21 Apr 2004 00:08:31 -0000
>> Subject: Re: calculate the number of logic gate in FPGA
>>
>>> After synthesis(Synplify Pro), I got how many LUTs I consumed,
>>> How to equally convert it to the number of logic gates? The device
>>> is the Xilinx VirtexE.
>>
>> Quick answer: There isn't any easy way. It depends upon how much
>> logic your design put in each LUT.
>>
>> Crazy question... What's the most number of gates that anybody
>> has ever put into a LUT? Might be a fun hack to try all possible
>> functions, translate to gates, maybe run some minimization stuff,
>> and remember the worst case.


>>
>> --
>> The suespammers.org mail server is located in California. So are all
>> my other mailboxes. Please do not send unsolicited bulk e-mail or
>> unsolicited commercial e-mail to my suespammers.org address or any of
>> my other addresses. These are my opinions, not necessarily my
>> employer's. I hate spam.
>>
>
>



--
|| Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
|| [email protected] PO Box 33091 ||
|| http://www.xess.com Raleigh NC 27636 USA FAX919) 367-2946 ||

>F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D +
> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D
>
>If you allow some of the outputs of the 2-input AND gates to be shared
>across minterms, then you can cut 8 AND gates and get down to 23 2-input
>gates.

That looks like odd parity, aka an XOR tree. If Peter's claim
of a (2 input?) XOR counting as 4 NANDs, then we can built it in
2 layers using 12 gates rather than 23. Did I miss something?



I'm assuming NOR and NAND count the same. Is that generally true?
How do ASIC people count inverters? A whole gate or a partial gate?
How about AND vs NAND? Do I get a free inverter sometimes?

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

> After synthesis(Synplify Pro), I got how many LUTs I consumed,
> How to equally convert it to the number of logic gates? The device is
> the Xilinx VirtexE.

I've got a similar problem:
I want to know how much Resources in my FPGA are used ...
so I'm not interested in the Gate-Count but in the number of
Flipflops, Luts, BRams ...

The Map-Report shows:
BRams 25 of 40
DFF 5200 of 10240
FGs 4200 of 10240


But I expected 28 Blockrams to be used so I opend the (routed)
design in the Floorplanner and there the usage was higher ...

Floorplanner says something like:
BRams 28 of 40
DFF 5800 of 10240
FGs 4500 of 10240



As I know the Number of used Blockrams I tend to say the
Florplanner is probably right - but whats wrong with my
map report??



I'm using Xilinx XST 5.2 for a Virtex-2-1000 ff896, but there is
the same problem in a project for a Spartan2-200


bye,
Michael

[email protected] (Hal Murray) wrote in
news:[email protected]:

>>F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D +
>> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D
>>
>>If you allow some of the outputs of the 2-input AND gates to be shared
>>across minterms, then you can cut 8 AND gates and get down to 23 2-input
>>gates.
>
> That looks like odd parity, aka an XOR tree. If Peter's claim
> of a (2 input?) XOR counting as 4 NANDs, then we can built it in
> 2 layers using 12 gates rather than 23. Did I miss something?

I agree with you on that. There must be more resource sharing that allows
you to reduce the 23 gates down to 12.


>
>
>
> I'm assuming NOR and NAND count the same. Is that generally true?
> How do ASIC people count inverters? A whole gate or a partial gate?
> How about AND vs NAND? Do I get a free inverter sometimes?
>



--
|| Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
|| [email protected] PO Box 33091 ||
|| http://www.xess.com Raleigh NC 27636 USA FAX919) 367-2946 ||

Just to indicate more sources of confusion:
A LUT used as a RAM is worth at least 4 gates per bit, plus decoding from 4
inputs to 16 cells. That gets us to ~80 gates.
If you use the LUT as a 16-bit shift register with adjustable tap (SRL16),
then you are well over a 100 gates per LUT.
But I will not tell Marketing...

14 years ago I quipped that gate-count is as meaningless a measure of FPGA
capacity, as 36-24-34 is a meaningless measure of female beauty.
May not be politically correct these days...
Peter Alfke
=====================
> From: Dave Vanden Bout <[email protected]>
> Organization: Road Runner - NC
> Newsgroups: comp.arch.fpga
> Date: Wed, 21 Apr 2004 12:12:15 GMT
> Subject: Re: calculate the number of logic gate in FPGA
>
> [email protected] (Hal Murray) wrote in
> news:[email protected]:
>
>>> F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D +
>>> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D
>>>
>>> If you allow some of the outputs of the 2-input AND gates to be shared
>>> across minterms, then you can cut 8 AND gates and get down to 23 2-input
>>> gates.
>>
>> That looks like odd parity, aka an XOR tree. If Peter's claim
>> of a (2 input?) XOR counting as 4 NANDs, then we can built it in
>> 2 layers using 12 gates rather than 23. Did I miss something?
>
> I agree with you on that. There must be more resource sharing that allows
> you to reduce the 23 gates down to 12.
>
>
>>
>>
>>
>> I'm assuming NOR and NAND count the same. Is that generally true?
>> How do ASIC people count inverters? A whole gate or a partial gate?
>> How about AND vs NAND? Do I get a free inverter sometimes?
>>
>
>
>
> --
> || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
> || [email protected] PO Box 33091 ||
> || http://www.xess.com Raleigh NC 27636 USA FAX919) 367-2946 ||

I wonder how the Mapper computes the gate count in the report file? It makes
me laugh reading a practically meaningless number quoted to 7 significant
figures!
Marketing, bless!
Syms.
"Peter Alfke" <[email protected]> wrote in message
news:BCABF524.5FA5%[email protected]...
> Just to indicate more sources of confusion:
> A LUT used as a RAM is worth at least 4 gates per bit, plus decoding from
4
> inputs to 16 cells. That gets us to ~80 gates.
> If you use the LUT as a 16-bit shift register with adjustable tap (SRL16),
> then you are well over a 100 gates per LUT.
> But I will not tell Marketing...
>
> 14 years ago I quipped that gate-count is as meaningless a measure of FPGA
> capacity, as 36-24-34 is a meaningless measure of female beauty.
> May not be politically correct these days...
> Peter Alfke

Not true. Marketing would have rounded it up to the next million.
it takes sofrware geeks to quote vaguely defined values with 7 digit
resolution, aka "accuracy".
Peter Alfke

> From: "Symon" <[email protected]>
> Newsgroups: comp.arch.fpga
> Date: Wed, 21 Apr 2004 10:39:22 -0700
> Subject: Re: calculate the number of logic gate in FPGA
>
> I wonder how the Mapper computes the gate count in the report file? It makes
> me laugh reading a practically meaningless number quoted to 7 significant
> figures!
> Marketing, bless!
> Syms.
> "Peter Alfke" <[email protected]> wrote in message
> news:BCABF524.5FA5%[email protected]...
>> Just to indicate more sources of confusion:
>> A LUT used as a RAM is worth at least 4 gates per bit, plus decoding from
> 4
>> inputs to 16 cells. That gets us to ~80 gates.
>> If you use the LUT as a 16-bit shift register with adjustable tap (SRL16),
>> then you are well over a 100 gates per LUT.
>> But I will not tell Marketing...
>>
>> 14 years ago I quipped that gate-count is as meaningless a measure of FPGA
>> capacity, as 36-24-34 is a meaningless measure of female beauty.
>> May not be politically correct these days...
>> Peter Alfke
>
>

[email protected] (Hal Murray) wrote in message news:<[email protected]>...
> >F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D +
> > A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D
> >
> >If you allow some of the outputs of the 2-input AND gates to be shared
> >across minterms, then you can cut 8 AND gates and get down to 23 2-input
> >gates.
>
> That looks like odd parity, aka an XOR tree. If Peter's claim
> of a (2 input?) XOR counting as 4 NANDs, then we can built it in
> 2 layers using 12 gates rather than 23. Did I miss something?
>
>

In almost any ASIC cell lib, an XOR can be as little as 1 2nand gate
for the elcheapo xfer common control version or usually about 2 2nand
gates worth of area for the much better aoi version. I could look up
the actual sizes for AMI,HP,VLSI but those are dated 0.6u. An inverter
usually costs about 70% of a 2nand. Its not the transister count but
the local interconnect that can make some of these bigger cells not so
big after all. Please forget about counting 2nand equivs. It makes no
sense for ASICs or FPGAs.

For most of my FPGA XST synth reports I look at the bigger functions
it finds, ie adders, Dflops, muxes etc and convert them directly into
their equiv ASIC by looking at the lib relative areas. Most of my
logic doesn't produce alot of those funny 4-8 functions that can't be
easily described or compared, its the memories, muxes, flops, adders
(maybe multipliers) that dominate.

>
> I'm assuming NOR and NAND count the same. Is that generally true?
> How do ASIC people count inverters? A whole gate or a partial gate?
> How about AND vs NAND? Do I get a free inverter sometimes?


Nand & Nor are usually 1 unit but Nands are much prefered over Nors
due to p being 1/2 strength of n fets. Inverter is 0.7 of 2nand.
And/Or might usually be 1.7 or possibly smaller say 1.5 for local
optimisation. Each cell generally has some cost just to insert power &
substrate hookup and DFlops, adders & bigger muxes are spared the
insertion cost by cramming as much as possible into the 1 fixed cost
per cell.


You can get some of this ASIC lib info from TLSI,UMC even Mosis and if
you ask nicely a sales guy will hand you the books, just don't say you
are using FPGAs.

regards

johnjakson_usa_com

john jakson wrote:

> [email protected] (Hal Murray) wrote:

>>>F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D +
>>> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D

Four input XOR was going to be my guess.

>>>If you allow some of the outputs of the 2-input AND gates to be shared
>>>across minterms, then you can cut 8 AND gates and get down to 23 2-input
>>>gates.

>>That looks like odd parity, aka an XOR tree. If Peter's claim
>>of a (2 input?) XOR counting as 4 NANDs, then we can built it in
>>2 layers using 12 gates rather than 23. Did I miss something?

As far as I know, gate counting in CMOS is the number of transistors
divided by four (the number for NAND2).

> In almost any ASIC cell lib, an XOR can be as little as 1 2nand gate
> for the elcheapo xfer common control version or usually about 2 2nand
> gates worth of area for the much better aoi version. I could look up
> the actual sizes for AMI,HP,VLSI but those are dated 0.6u. An inverter
> usually costs about 70% of a 2nand. Its not the transister count but
> the local interconnect that can make some of these bigger cells not so
> big after all. Please forget about counting 2nand equivs. It makes no
> sense for ASICs or FPGAs.

Transistors divided by four is slightly different from a logic point
of view, but seems reasonable to me.

(snip)

>>I'm assuming NOR and NAND count the same. Is that generally true?
>>How do ASIC people count inverters? A whole gate or a partial gate?
>>How about AND vs NAND? Do I get a free inverter sometimes?

> Nand & Nor are usually 1 unit but Nands are much prefered over Nors
> due to p being 1/2 strength of n fets. Inverter is 0.7 of 2nand.
> And/Or might usually be 1.7 or possibly smaller say 1.5 for local
> optimisation. Each cell generally has some cost just to insert power &
> substrate hookup and DFlops, adders & bigger muxes are spared the
> insertion cost by cramming as much as possible into the 1 fixed cost
> per cell.

For TTL, NAND is much simpler than AND and OR, which are simpler
than NOR. For CMOS, other than the difference above, I believe
that NAND, NOR, AND, OR all take the same number of transistors.

> You can get some of this ASIC lib info from TLSI,UMC even Mosis and if
> you ask nicely a sales guy will hand you the books, just don't say you
> are using FPGAs.

I would say that a fair way to count the gates is to generate
the CMOS ASIC logic, count the transistors, and divide by four.

One could do this for many designs that would fit into a given FPGA,
and average the results.

-- glen

Dave Vanden Bout <[email protected]> wrote in message

> A 4-input truth-table can be represented by a 16-node hypercube. You can
> select 8 nodes of the 16 such that none of these selected nodes are
> adjacent. Each of these nodes represents a 4-input minterm and since
> they are non-adjacent there is no possibility of combining minterms. A

Dave Vanden Bout <[email protected]> wrote in message news:<[email protected]>...
> [email protected] (Hal Murray) wrote in
> news:[email protected]:
>
> >>F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D +
> >> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D
> >>
> >>If you allow some of the outputs of the 2-input AND gates to be shared
> >>across minterms, then you can cut 8 AND gates and get down to 23 2-input
> >>gates.
> >
> > That looks like odd parity, aka an XOR tree. If Peter's claim
> > of a (2 input?) XOR counting as 4 NANDs, then we can built it in
> > 2 layers using 12 gates rather than 23. Did I miss something?
>
> I agree with you on that. There must be more resource sharing that allows
> you to reduce the 23 gates down to 12.

The hypercube reasoning is fascinating. I think what it missed is
that XOR allows you to combine non-adjacent nodes (ie 10 is not adjacent
to 01).

My two cents,
-rajeev-

And of course, any engineer worth his salt codes a little differently when
targetting an FPGA as opposed to targetting an ASIC. An experienced designer
knows the structure of the FPGA and tries to ensure the design fits it well.
An ASIC designer has a different set of library components on offer to the
designer. This means a comparison between FPGA LUT/FF/BRAM/MULT counts and
ASIC gate counts has little value.
IMO, Syms.
"john jakson" <[email protected]> wrote in message
news:[email protected] om...
> For most of my FPGA XST synth reports I look at the bigger functions
> it finds, ie adders, Dflops, muxes etc and convert them directly into
> their equiv ASIC by looking at the lib relative areas. Most of my
> logic doesn't produce alot of those funny 4-8 functions that can't be
> easily described or compared, its the memories, muxes, flops, adders
> (maybe multipliers) that dominate.
>