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Old 04-16-2006, 07:17 PM
Yaseen Zaidi
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Default Boolean as port type

Hello all,

I take one of the ports as type Boolean in a VHDL module using Xilinx
ISE. The code synthesizes and would also translate and map, but for
post PAR simulation, Modelsim is sullen on type mismatch between
component and entity for concerned Boolean port.

It seems that VITAL simprim libraries do not support Boolean ports.
Please share your experience.



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