FPGA Central

Hello,

First of all I will make my question: Could you please say me how
many Masters can be connected to the Bus when the BFM simulation is
been used?

I created a coprocessor for the embedded PowerPC, and two files to
implement a bridge between the PLB Bus and the Bus of my coprocessor
( small bus called On Chip Bus).
I have a Master which is able to read all the operations from a txt
file. this is my sistem

BFM Bus
file.txt --> Master_1 -->|
|
|-->bridge_plb2ocb
|
coprocessor(bus on chip bus ocb)
|-->bridge_ocb2plb
|
Register<--|

I am using the BFM simulation because I got always problems with the
behavioural simulation( i have a problem that i posted here and i do
not have the solution yet(
http://groups.google.com/group/comp....98d98a5af6caf8
))


The point is that Master_1 and bridge_ocb2plb are both masters and the
system it is not working. Only the master that is mapped in the memory
address 0x00000000 it is working. I checked first with Master_1 mapped
in 0x0, and later with bridge_ocb2plb mapped in 0x0, and the bus of
the BFM simulation only answer or hear the request of one of both
masters, the one which is mapped in the 0x0.

I think that you have more experience with embedded systems, do you
think that what i am writing here make sense? It is possible that the
BFM simulation only allow to have one Master in our systems? Is there
another possibility to simulate a system with 2,3 or more masters?


Thank you very much for your answers.

Note: if the solution it is to use the behaviural simulation, could
you please help my with my problem using this simulation, i have post
it here with the Subject:
XPS behavioral simulation fails: the design is not loaded

"ferorcue" <[email protected]> wrote in message
news:[email protected] oups.com...
> Hello,
>
> First of all I will make my question: Could you please say me how
> many Masters can be connected to the Bus when the BFM simulation is
> been used?
>
> I created a coprocessor for the embedded PowerPC, and two files to
> implement a bridge between the PLB Bus and the Bus of my coprocessor
> ( small bus called On Chip Bus).
> I have a Master which is able to read all the operations from a txt
> file. this is my sistem
>
> BFM Bus
> file.txt --> Master_1 -->|
> |
> |-->bridge_plb2ocb
> |
> coprocessor(bus on chip bus ocb)
> |-->bridge_ocb2plb
> |
> Register<--|
>
> I am using the BFM simulation because I got always problems with the
> behavioural simulation( i have a problem that i posted here and i do
> not have the solution yet(
> http://groups.google.com/group/comp....98d98a5af6caf8
> ))
>
>
> The point is that Master_1 and bridge_ocb2plb are both masters and the
> system it is not working. Only the master that is mapped in the memory
> address 0x00000000 it is working. I checked first with Master_1 mapped
> in 0x0, and later with bridge_ocb2plb mapped in 0x0, and the bus of
> the BFM simulation only answer or hear the request of one of both
> masters, the one which is mapped in the 0x0.
>
> I think that you have more experience with embedded systems, do you
> think that what i am writing here make sense? It is possible that the
> BFM simulation only allow to have one Master in our systems? Is there
> another possibility to simulate a system with 2,3 or more masters?
>
>
> Thank you very much for your answers.
>
> Note: if the solution it is to use the behaviural simulation, could
> you please help my with my problem using this simulation, i have post
> it here with the Subject:
> XPS behavioral simulation fails: the design is not loaded
>

In general, a bus structure will support multiple masters. You will require
some arbitration logic and some muxing logic to mux the winning master onto
the bus. Does the bus protocol you are using support arbitartion
(request/grant sort of thing)?

Mike