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  #1 (permalink)  
Old 11-28-2007, 07:37 AM
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Default Behavioral Simulation working but Post-route Simulation is not.

Hi,

I have been working on a project and get the coding done and tested
using Behavioral Simulation. However, I download it into the
FPGA(Spartan 3), it wouldn't work. So I went back and discovered that
the Post-route Simulation are all wrong. I had not encountered this
before. What could be the source of the problem? Or is there specific
areas which I could look at?

BTW, I am using Xilinx ISE 9.2i.

Thank You
Andy
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  #2 (permalink)  
Old 11-28-2007, 08:12 AM
mk
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Default Re: Behavioral Simulation working but Post-route Simulation is not.

On Tue, 27 Nov 2007 23:37:58 -0800 (PST), "[email protected]"
<[email protected]> wrote:

>Hi,
>
>I have been working on a project and get the coding done and tested
>using Behavioral Simulation. However, I download it into the
>FPGA(Spartan 3), it wouldn't work. So I went back and discovered that
>the Post-route Simulation are all wrong. I had not encountered this
>before. What could be the source of the problem? Or is there specific
>areas which I could look at?


Most probably you're not meeting timing. Does it help if you run the
design at a slower speed? It might be easier to check the simulation
for lower speed.
Check the timing reports. Also make sure that your constraints are
setup correctly (all clocks defined, clock relationships defined,
false paths added, multi-cycle paths multiply checked).
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  #3 (permalink)  
Old 11-28-2007, 10:03 AM
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Default Re: Behavioral Simulation working but Post-route Simulation is not.

On Nov 28, 4:12 pm, mk <kal*@dspia.*comdelete> wrote:
> On Tue, 27 Nov 2007 23:37:58 -0800 (PST), "[email protected]"
>
> <[email protected]> wrote:
> >Hi,

>
> >I have been working on a project and get the coding done and tested
> >using Behavioral Simulation. However, I download it into the
> >FPGA(Spartan 3), it wouldn't work. So I went back and discovered that
> >the Post-route Simulation are all wrong. I had not encountered this
> >before. What could be the source of the problem? Or is there specific
> >areas which I could look at?

>
> Most probably you're not meeting timing. Does it help if you run the
> design at a slower speed? It might be easier to check the simulation
> for lower speed.
> Check the timing reports. Also make sure that your constraints are
> setup correctly (all clocks defined, clock relationships defined,
> false paths added, multi-cycle paths multiply checked).


I had actually set to clk to a a very slow one. From the timing
reports, I had actually meet all constrains and my design only use a
single clock.
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  #4 (permalink)  
Old 11-28-2007, 12:18 PM
mh
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Default Re: Behavioral Simulation working but Post-route Simulation is not.

On Nov 28, 3:03 pm, "[email protected]" <[email protected]> wrote:
> On Nov 28, 4:12 pm, mk <kal*@dspia.*comdelete> wrote:
>
>
>
>
>
> > On Tue, 27 Nov 2007 23:37:58 -0800 (PST), "[email protected]"

>
> > <[email protected]> wrote:
> > >Hi,

>
> > >I have been working on a project and get the coding done and tested
> > >using Behavioral Simulation. However, I download it into the
> > >FPGA(Spartan 3), it wouldn't work. So I went back and discovered that
> > >the Post-route Simulation are all wrong. I had not encountered this
> > >before. What could be the source of the problem? Or is there specific
> > >areas which I could look at?

>
> > Most probably you're not meeting timing. Does it help if you run the
> > design at a slower speed? It might be easier to check the simulation
> > for lower speed.
> > Check the timing reports. Also make sure that your constraints are
> > setup correctly (all clocks defined, clock relationships defined,
> > false paths added, multi-cycle paths multiply checked).

>
> I had actually set to clk to a a very slow one. From the timing
> reports, I had actually meet all constrains and my design only use a
> single clock.- Hide quoted text -
>
> - Show quoted text -



Andy,

Check pad report as well.

/MH
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  #5 (permalink)  
Old 11-28-2007, 12:38 PM
KJ
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Default Re: Behavioral Simulation working but Post-route Simulation is not.


<[email protected]> wrote in message
news:[email protected]...
> On Nov 28, 4:12 pm, mk <kal*@dspia.*comdelete> wrote:
>> On Tue, 27 Nov 2007 23:37:58 -0800 (PST), "[email protected]"
>>
>> <[email protected]> wrote:
>> >Hi,

>>
>> >I have been working on a project and get the coding done and tested
>> >using Behavioral Simulation. However, I download it into the
>> >FPGA(Spartan 3), it wouldn't work. So I went back and discovered that
>> >the Post-route Simulation are all wrong. I had not encountered this
>> >before. What could be the source of the problem? Or is there specific
>> >areas which I could look at?

>>
>> Most probably you're not meeting timing. Does it help if you run the
>> design at a slower speed? It might be easier to check the simulation
>> for lower speed.
>> Check the timing reports. Also make sure that your constraints are
>> setup correctly (all clocks defined, clock relationships defined,
>> false paths added, multi-cycle paths multiply checked).

>
> I had actually set to clk to a a very slow one. From the timing
> reports, I had actually meet all constrains and my design only use a
> single clock.


Post-route simulations fail for only one reason...timing.
- Does your testbench model the FPGA inputs with the proper setup and hold
times? 'Proper' meaning it models the real world system which is also
failing.
- Any asynchronous clocking going on? i.e. The clock input of a flip flop
is the output of some other combinatorial logic or a flip flop? A purely
synchronous design wouldn't have this approach, since you say you're running
at a 'slow' clock speed, I'm guessing that you're violating a hold time
requirement (which will happen independent of clock speed). Violating a
hold time requirement is darn near impossible in an FPGA with a synchronous
design but very easy when you have gated clocks being generated internallly.

KJ


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