FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-29-2007, 11:46 AM
Guest
 
Posts: n/a
Default Asynchronous FIFO and almost empty - bug?

Hi,

we are using an asynchronous FIFO to bridge two clock domains. Both
domains have "the same" clock speed but different clock oscillators.

We shift data phits in the FIFO which always form a data packet. In
between a packet data is shifted in continously without a break.
Breaks (no shift in) are only allowed in between packets.
On the output side of the FIFO we need a steady data stream during a
data packet. The packet may not be interrupted. As the input side may
be slower we start shift-out data if at least two data phits are in
the FIFO. As the 2 clocks have almost the same frequency this
guarantees that we never have a buffer underflow.

The problem we found is that the almost empty flag is only asserted if
the FIFO is beeing emptied and not if it is beeing filled. So if the
FIFO was empty and we get a shift in the almost empty is not asserted
although we set the treshold to one. Is this a bug?

We tried to solve that problem by generating a delay-empty signal at
the output which guarantees that if the FIFO was emtpy and than
receives a shift in we still wait another cycle so we get another
shift in to avoid underflow.

This solution however does not solve the problem if the FIFO exactly
had one entry when starting to shift out a packet. In this case
neither delayed-empty nor almost empty is asserted, hence we get an
underflow.

Why isn't the almost empty signal asserted every time there is a
single packet in the FIFO? Ideas?
Reply With Quote
  #2 (permalink)  
Old 11-29-2007, 04:35 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

On Nov 29, 3:46 am, "[email protected]"
<[email protected]> wrote:
> Hi,
>
> we are using an asynchronous FIFO to bridge two clock domains. Both
> domains have "the same" clock speed but different clock oscillators.
>
> We shift data phits in the FIFO which always form a data packet. In
> between a packet data is shifted in continously without a break.
> Breaks (no shift in) are only allowed in between packets.
> On the output side of the FIFO we need a steady data stream during a
> data packet. The packet may not be interrupted. As the input side may
> be slower we start shift-out data if at least two data phits are in
> the FIFO. As the 2 clocks have almost the same frequency this
> guarantees that we never have a buffer underflow.
>
> The problem we found is that the almost empty flag is only asserted if
> the FIFO is beeing emptied and not if it is beeing filled. So if the
> FIFO was empty and we get a shift in the almost empty is not asserted
> although we set the treshold to one. Is this a bug?

Which FPGA family, which type of FIFO controller, and also what clock
rate?
Peter Alfke, Xilinx Applications>


> We tried to solve that problem by generating a delay-empty signal at
> the output which guarantees that if the FIFO was emtpy and than
> receives a shift in we still wait another cycle so we get another
> shift in to avoid underflow.
>
> This solution however does not solve the problem if the FIFO exactly
> had one entry when starting to shift out a packet. In this case
> neither delayed-empty nor almost empty is asserted, hence we get an
> underflow.
>
> Why isn't the almost empty signal asserted every time there is a
> single packet in the FIFO? Ideas?


Reply With Quote
  #3 (permalink)  
Old 11-29-2007, 05:26 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

On Nov 29, 3:46 am, "[email protected]"
<[email protected]> wrote:
> Hi,
>
> we are using an asynchronous FIFO to bridge two clock domains. Both
> domains have "the same" clock speed but different clock oscillators.
>
> We shift data phits in the FIFO which always form a data packet. In
> between a packet data is shifted in continously without a break.
> Breaks (no shift in) are only allowed in between packets.
> On the output side of the FIFO we need a steady data stream during a
> data packet. The packet may not be interrupted. As the input side may
> be slower we start shift-out data if at least two data phits are in
> the FIFO. As the 2 clocks have almost the same frequency this
> guarantees that we never have a buffer underflow.
>
> The problem we found is that the almost empty flag is only asserted if
> the FIFO is beeing emptied and not if it is beeing filled. So if the
> FIFO was empty and we get a shift in the almost empty is not asserted
> although we set the treshold to one. Is this a bug?

In a synchronous (single-clock) FIFO, flag control is very simple,
done by a synchronous state machine.
With asynchronous (unrelated clocks) operation, flag control is very
complex, if metastable posssibilities must also be considered.
Almost Empty is generally considered a warning flag that can have a
one-count ambiguity.
Empty is the most important flag, and its rising edge is not allowed
to have any uncertainty. The trailing edge of EMPTY, however, often
has an additional delay, so as to avoid metastability.
My advice: trust the rising edge of the Empty flag, expect its falling
edge to have an additional pipeline delay, and treat the Almost Empty
flag just as a warning.
Peter Alfke


> We tried to solve that problem by generating a delay-empty signal at
> the output which guarantees that if the FIFO was emtpy and than
> receives a shift in we still wait another cycle so we get another
> shift in to avoid underflow.
>
> This solution however does not solve the problem if the FIFO exactly
> had one entry when starting to shift out a packet. In this case
> neither delayed-empty nor almost empty is asserted, hence we get an
> underflow.
>
> Why isn't the almost empty signal asserted every time there is a
> single packet in the FIFO? Ideas?


Reply With Quote
  #4 (permalink)  
Old 11-30-2007, 08:44 AM
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

Hi Peter,

we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was
generated with coregen 3.5. We just found out that there have been
several modifications regarding the almost empty signal in coregen
4.2. We'll try that out first.

Point is we NEED an almost empty signal at threshold == 1 which we can
rely on 100%. If I understand you correctly this is not given with the
Xilinx sync FIFOs so we would have to build our own, right?

regards, Heiner

On Nov 29, 5:35 pm, Peter Alfke <[email protected]> wrote:
> On Nov 29, 3:46 am, "[email protected]"
>
> <[email protected]> wrote:
> > Hi,

>
> > we are using an asynchronous FIFO to bridge two clock domains. Both
> > domains have "the same" clock speed but different clock oscillators.

>
> > We shift data phits in the FIFO which always form a data packet. In
> > between a packet data is shifted in continously without a break.
> > Breaks (no shift in) are only allowed in between packets.
> > On the output side of the FIFO we need a steady data stream during a
> > data packet. The packet may not be interrupted. As the input side may
> > be slower we start shift-out data if at least two data phits are in
> > the FIFO. As the 2 clocks have almost the same frequency this
> > guarantees that we never have a buffer underflow.

>
> > The problem we found is that the almost empty flag is only asserted if
> > the FIFO is beeing emptied and not if it is beeing filled. So if the
> > FIFO was empty and we get a shift in the almost empty is not asserted
> > although we set the treshold to one. Is this a bug?

>
> Which FPGA family, which type of FIFO controller, and also what clock
> rate?
> Peter Alfke, Xilinx Applications>
>
> > We tried to solve that problem by generating a delay-empty signal at
> > the output which guarantees that if the FIFO was emtpy and than
> > receives a shift in we still wait another cycle so we get another
> > shift in to avoid underflow.

>
> > This solution however does not solve the problem if the FIFO exactly
> > had one entry when starting to shift out a packet. In this case
> > neither delayed-empty nor almost empty is asserted, hence we get an
> > underflow.

>
> > Why isn't the almost empty signal asserted every time there is a
> > single packet in the FIFO? Ideas?


Reply With Quote
  #5 (permalink)  
Old 11-30-2007, 03:02 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

On Nov 30, 12:44 am, "[email protected]"
<[email protected]> wrote:
> Hi Peter,
>
> we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was
> generated with coregen 3.5. We just found out that there have been
> several modifications regarding the almost empty signal in coregen
> 4.2. We'll try that out first.
>
> Point is we NEED an almost empty signal at threshold == 1 which we can
> rely on 100%. If I understand you correctly this is not given with the
> Xilinx sync FIFOs so we would have to build our own, right?
>
> regards, Heiner
>
> On Nov 29, 5:35 pm, Peter Alfke <[email protected]> wrote:
>
> > On Nov 29, 3:46 am, "[email protected]"

>
> > <[email protected]> wrote:
> > > Hi,

>
> > > we are using an asynchronous FIFO to bridge two clock domains. Both
> > > domains have "the same" clock speed but different clock oscillators.

>
> > > We shift data phits in the FIFO which always form a data packet. In
> > > between a packet data is shifted in continously without a break.
> > > Breaks (no shift in) are only allowed in between packets.
> > > On the output side of the FIFO we need a steady data stream during a
> > > data packet. The packet may not be interrupted. As the input side may
> > > be slower we start shift-out data if at least two data phits are in
> > > the FIFO. As the 2 clocks have almost the same frequency this
> > > guarantees that we never have a buffer underflow.

>
> > > The problem we found is that the almost empty flag is only asserted if
> > > the FIFO is beeing emptied and not if it is beeing filled. So if the
> > > FIFO was empty and we get a shift in the almost empty is not asserted
> > > although we set the treshold to one. Is this a bug?

>
> > Which FPGA family, which type of FIFO controller, and also what clock
> > rate?
> > Peter Alfke, Xilinx Applications>

>
> > > We tried to solve that problem by generating a delay-empty signal at
> > > the output which guarantees that if the FIFO was emtpy and than
> > > receives a shift in we still wait another cycle so we get another
> > > shift in to avoid underflow.

>
> > > This solution however does not solve the problem if the FIFO exactly
> > > had one entry when starting to shift out a packet. In this case
> > > neither delayed-empty nor almost empty is asserted, hence we get an
> > > underflow.

>
> > > Why isn't the almost empty signal asserted every time there is a
> > > single packet in the FIFO? Ideas?


Reply With Quote
  #6 (permalink)  
Old 11-30-2007, 03:05 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

As I wrote, the problem is easy to solve for the synchronous case
(identical clocks) but difficult or impossible to solve for the
asynchronous case.
You wrote synchronous ???
Peter Alfke

On Nov 30, 12:44 am, "[email protected]"
<[email protected]> wrote:
> Hi Peter,
>
> we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was
> generated with coregen 3.5. We just found out that there have been
> several modifications regarding the almost empty signal in coregen
> 4.2. We'll try that out first.
>
> Point is we NEED an almost empty signal at threshold == 1 which we can
> rely on 100%. If I understand you correctly this is not given with the
> Xilinx sync FIFOs so we would have to build our own, right?
>
> regards, Heiner
>
> On Nov 29, 5:35 pm, Peter Alfke <[email protected]> wrote:
>
> > On Nov 29, 3:46 am, "[email protected]"

>
> > <[email protected]> wrote:
> > > Hi,

>
> > > we are using an asynchronous FIFO to bridge two clock domains. Both
> > > domains have "the same" clock speed but different clock oscillators.

>
> > > We shift data phits in the FIFO which always form a data packet. In
> > > between a packet data is shifted in continously without a break.
> > > Breaks (no shift in) are only allowed in between packets.
> > > On the output side of the FIFO we need a steady data stream during a
> > > data packet. The packet may not be interrupted. As the input side may
> > > be slower we start shift-out data if at least two data phits are in
> > > the FIFO. As the 2 clocks have almost the same frequency this
> > > guarantees that we never have a buffer underflow.

>
> > > The problem we found is that the almost empty flag is only asserted if
> > > the FIFO is beeing emptied and not if it is beeing filled. So if the
> > > FIFO was empty and we get a shift in the almost empty is not asserted
> > > although we set the treshold to one. Is this a bug?

>
> > Which FPGA family, which type of FIFO controller, and also what clock
> > rate?
> > Peter Alfke, Xilinx Applications>

>
> > > We tried to solve that problem by generating a delay-empty signal at
> > > the output which guarantees that if the FIFO was emtpy and than
> > > receives a shift in we still wait another cycle so we get another
> > > shift in to avoid underflow.

>
> > > This solution however does not solve the problem if the FIFO exactly
> > > had one entry when starting to shift out a packet. In this case
> > > neither delayed-empty nor almost empty is asserted, hence we get an
> > > underflow.

>
> > > Why isn't the almost empty signal asserted every time there is a
> > > single packet in the FIFO? Ideas?


Reply With Quote
  #7 (permalink)  
Old 11-30-2007, 07:31 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

On Nov 30, 12:44 am, "[email protected]"
<[email protected]> wrote:
> Hi Peter,
>
> we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was
> generated with coregen 3.5. We just found out that there have been
> several modifications regarding the almost empty signal in coregen
> 4.2. We'll try that out first.
>
> Point is we NEED an almost empty signal at threshold == 1 which we can
> rely on 100%. If I understand you correctly this is not given with the
> Xilinx sync FIFOs so we would have to build our own, right?
>
> regards, Heiner
>
> On Nov 29, 5:35 pm, Peter Alfke <[email protected]> wrote:
>
> > On Nov 29, 3:46 am, "[email protected]"

>
> > <[email protected]> wrote:
> > > Hi,

>
> > > we are using an asynchronous FIFO to bridge two clock domains. Both
> > > domains have "the same" clock speed but different clock oscillators.

>
> > > We shift data phits in the FIFO which always form a data packet. In
> > > between a packet data is shifted in continously without a break.
> > > Breaks (no shift in) are only allowed in between packets.
> > > On the output side of the FIFO we need a steady data stream during a
> > > data packet. The packet may not be interrupted. As the input side may
> > > be slower we start shift-out data if at least two data phits are in
> > > the FIFO. As the 2 clocks have almost the same frequency this
> > > guarantees that we never have a buffer underflow.

>
> > > The problem we found is that the almost empty flag is only asserted if
> > > the FIFO is beeing emptied and not if it is beeing filled. So if the
> > > FIFO was empty and we get a shift in the almost empty is not asserted
> > > although we set the treshold to one. Is this a bug?

>
> > Which FPGA family, which type of FIFO controller, and also what clock
> > rate?
> > Peter Alfke, Xilinx Applications>

Heiner, if you have questions about asynchronous FIFOs, just send me
an e-mail.
English oder Deutsch. But I'll be on vacation starting next Tuesday.
Peter Alfke ([email protected])

> > > We tried to solve that problem by generating a delay-empty signal at
> > > the output which guarantees that if the FIFO was emtpy and than
> > > receives a shift in we still wait another cycle so we get another
> > > shift in to avoid underflow.

>
> > > This solution however does not solve the problem if the FIFO exactly
> > > had one entry when starting to shift out a packet. In this case
> > > neither delayed-empty nor almost empty is asserted, hence we get an
> > > underflow.

>
> > > Why isn't the almost empty signal asserted every time there is a
> > > single packet in the FIFO? Ideas?


Reply With Quote
  #8 (permalink)  
Old 12-03-2007, 04:53 AM
PatC
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

Peter Alfke wrote:
> On Nov 29, 3:46 am, "[email protected]"
>> The problem we found is that the almost empty flag is only asserted if
>> the FIFO is beeing emptied and not if it is beeing filled. So if the
>> FIFO was empty and we get a shift in the almost empty is not asserted
>> although we set the treshold to one. Is this a bug?


You could use the fifo read count and compare it to 1? The latency may
be higher, but it's guarantied there'll be a point there when it asserts.

HTH,
[email protected]
Reply With Quote
  #9 (permalink)  
Old 12-03-2007, 05:35 AM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

On Dec 2, 8:53 pm, PatC <[email protected]> wrote:
> Peter Alfke wrote:
> > On Nov 29, 3:46 am, "[email protected]"
> >> The problem we found is that the almost empty flag is only asserted if
> >> the FIFO is beeing emptied and not if it is beeing filled. So if the
> >> FIFO was empty and we get a shift in the almost empty is not asserted
> >> although we set the treshold to one. Is this a bug?

>
> You could use the fifo read count and compare it to 1? The latency may
> be higher, but it's guarantied there'll be a point there when it asserts.
>
> HTH,
> [email protected]


In an asynchronous FIFO, the flags must be synchronized to the
appropriate clock.
The leading edge of Almost Empty is normally generated by the read
clock, and it is the read side that usually worries about (Almost)
Empty. The trailing edge, however, is generated by the write clock,
and (for most purposes) needs re-synchronization to the read clock.
That re-synchronization needs an extra clock edge (or two) to avoid
metastable confusion.
The basic problem is the unknown phase relationship between the two
clocks. The edges can be far apart, but also very close to each other,
down to fractional picoseconds. But the controller has to provide
correct flag outputs. The actual reading and writing is trivial, as
long as the RAM is dual-ported.
Peter Alfke
Reply With Quote
  #10 (permalink)  
Old 12-03-2007, 08:20 AM
Guest
 
Posts: n/a
Default Re: Asynchronous FIFO and almost empty - bug?

HI

as stated we are using the FIFO in an Asynchronous way. The read and
write clock are both 200 MHz but are provided through 2 different
oscillators. We are using the almost empty signal onlyin the read
clock domain. We are currently implementing a single FF stage located
at the output side of the FIFO. If then the FIFO goes empty (and the
empty signal behaves correctly) we can be sure to have another datum
in the FF stage, equaling almost empty.

hope this helps..

regs, Heiner
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Asynchronous FIFO with depth that is not a power of 2 googler Verilog 6 05-15-2008 10:10 AM
Fifo Block-RAM Xilinx ISE - port empty zlotawy FPGA 0 11-24-2007 10:23 AM
Asynchronous FIFO Latency. RaKa FPGA 1 11-13-2007 03:09 AM
asynchronous FIFO design kelvins FPGA 3 04-10-2006 07:35 PM
Asynchronous FIFO design question [email protected] FPGA 12 03-08-2006 04:32 PM


All times are GMT +1. The time now is 04:26 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved