FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 05-27-2005, 03:12 AM
Jim George
Guest
 
Posts: n/a
Default Async FIFO coregen wizard

I have tried to instantiate the Asynchronous FIFO core (v6) from
Coregen, and it's been giving me trouble. First, I can't get it to
produce a FIFO using distributed RAM (I wanted a 31-deep FIFO). When I
try, it tells me there is a block RAM in the usage summary. If I try to
open the core again after it's generated, it sometimes just beeps and
exits (no error messages at all), sometimes it goes into the coregen
wizard with "Block RAM" selected and the FIFO depth some enormous value
like 65536.

I am using ISE 6.3.03i, with the latest IP core updates installed.

If it was a synch. FIFO, I have my own core, but I need an Async FIFO to
cross clock domains and I dont want to waste a BRAM site.

-Jim
Reply With Quote
  #2 (permalink)  
Old 05-27-2005, 09:48 PM
Guest
 
Posts: n/a
Default Re: Async FIFO coregen wizard

Jim-

> I have tried to instantiate the Asynchronous FIFO core (v6) from
> Coregen, and it's been giving me trouble. First, I can't get it to
> produce a FIFO using distributed RAM (I wanted a 31-deep FIFO). When I
> try, it tells me there is a block RAM in the usage summary.


We have often dealt with the same issue. You can have distributed Ram
selected, but it still uses block ram. Our solution has been to always
click the dist ram button before generating - even if it is already
selected. Also always check "view core footprint" to see if it used
block ram or dist ram. If block ram, try again. Silly, but this issue
has been there since at least version 4, and is still there in v6.1.
Luckily you only have to get it to generate properly once...

Jason Daughenbaugh
http://www.advanced.pro

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Questions about Async. FIFO [email protected] Verilog 0 01-17-2006 11:42 AM
Best Async FIFO Implementation Davy Verilog 10 11-11-2005 01:18 AM
How to determine number of block rams in a Coregen Fifo rootz Verilog 4 06-11-2005 06:35 PM
Async FIFO problem... Paul Davis FPGA 13 03-10-2005 09:40 AM
Using a BlockRam in an async FIFO for bus width conversion ? Arnaud FPGA 3 06-28-2004 06:33 PM


All times are GMT +1. The time now is 12:05 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved