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  #1 (permalink)  
Old 04-26-2006, 05:24 AM
Jim Granville
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Default Async FPGA ~2GHz

For those interested in Async devices, and uses :

http://www.achronix.com/news.html?ne...69ce9b919f7562

It is a way's off being usable, but the numbers are impressive

No mention of device size, but the info suggests they target the
high-price/low volume user space.
[ Not too many customers need -196'C ]

... and no mention of design tools, which may prove to be a bigger
challenge than the silicon.

-jg


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  #2 (permalink)  
Old 04-26-2006, 09:10 AM
Uwe Bonnes
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Default Re: Async FPGA ~2GHz

Jim Granville <[email protected]> wrote:
> For those interested in Async devices, and uses :


> http://www.achronix.com/news.html?ne...69ce9b919f7562


> It is a way's off being usable, but the numbers are impressive


> No mention of device size, but the info suggests they target the
> high-price/low volume user space.
> [ Not too many customers need -196'C ]


Jim, the press release tells about testing from -196C to +130C not only at
-196 C...

> .. and no mention of design tools, which may prove to be a bigger
> challenge than the silicon.


--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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  #3 (permalink)  
Old 04-26-2006, 10:29 AM
Jim Granville
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Default Re: Async FPGA ~2GHz

Uwe Bonnes wrote:
> Jim Granville <[email protected]> wrote:
>
>>For those interested in Async devices, and uses :

>
>
>>http://www.achronix.com/news.html?ne...69ce9b919f7562

>
>
>>It is a way's off being usable, but the numbers are impressive

>
>
>> No mention of device size, but the info suggests they target the
>>high-price/low volume user space.
>> [ Not too many customers need -196'C ]

>
>
> Jim, the press release tells about testing from -196C to +130C not only at
> -196 C...


I realise that, of course, - the comment still stands :
Do you have an app that needs to go to -196'C ?
Mars is the only deployment I can think of, most others are
covered by the terrestrial Military -55'C - 125'C range.

-jg

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  #4 (permalink)  
Old 04-26-2006, 12:40 PM
Bevan Weiss
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Default Re: Async FPGA ~2GHz

Jim Granville wrote:
> For those interested in Async devices, and uses :
>
> http://www.achronix.com/news.html?ne...69ce9b919f7562
>
>
> It is a way's off being usable, but the numbers are impressive
>
> No mention of device size, but the info suggests they target the
> high-price/low volume user space.
> [ Not too many customers need -196'C ]
>
> .. and no mention of design tools, which may prove to be a bigger
> challenge than the silicon.
>
> -jg


I'm amazed they have achieved this operation over the 0.2V - 3.9V supply
range. 0.2V is not much voltage at all... I would have thought
transistor threshold voltages would have caused issues at such a low
voltage. How are they achieving such low threshold voltages?


Bevan
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  #5 (permalink)  
Old 04-26-2006, 02:03 PM
dp
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Default Re: Async FPGA ~2GHz

> I'm amazed they have achieved this operation over the 0.2V - 3.9V supply
> range. 0.2V is not much voltage at all... I would have thought
> transistor threshold voltages would have caused issues at such a low
> voltage. How are they achieving such low threshold voltages?


Sounds interesting to me as well, perhaps some of the other 90nm
manufacturers could shed some light - does it really work? Probably
not at full speed, but even at DC - do the FETs really turn on at 0.2
V?
While I am not sure what this synchronous/asynchronous gimmick is
all about I would say I am glad they may soon have a marketable
alternative to the rest of the makers, I guess they all became a bit
too big to talk to (and stay innovative).

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


Bevan Weiss wrote:
> Jim Granville wrote:
> > For those interested in Async devices, and uses :
> >
> > http://www.achronix.com/news.html?ne...69ce9b919f7562
> >
> >
> > It is a way's off being usable, but the numbers are impressive
> >
> > No mention of device size, but the info suggests they target the
> > high-price/low volume user space.
> > [ Not too many customers need -196'C ]
> >
> > .. and no mention of design tools, which may prove to be a bigger
> > challenge than the silicon.
> >
> > -jg

>
> I'm amazed they have achieved this operation over the 0.2V - 3.9V supply
> range. 0.2V is not much voltage at all... I would have thought
> transistor threshold voltages would have caused issues at such a low
> voltage. How are they achieving such low threshold voltages?
>
>
> Bevan


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  #6 (permalink)  
Old 04-26-2006, 04:13 PM
Austin Lesea
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Posts: n/a
Default Re: Async FPGA ~2GHz

dp,

Even Intel has realized that frequency kills. Not sure why they are so
excited about touting 2 GHz.

The fets are running in "active mode" basically just behaving as analog
(low gain) transistor amplifiers in their sub threshold regions...kinda
on, kinda off, kinda inbetween.

I am sure that the speed of operation is very slow down at 0.2V.

At 3.9 volts on a 90nm transistor, I am guessing the lifetime to
breakdown is about a week, or sooner.

I'd like to see them get block RAM, processors, DLL's/PLL's, MGTs, etc.
to work in the same fashion. I am sure we all know the stories of the
attempts at making async microprocessors, and how they were abandoned
for having far too much area, and no real performance benefits.

And when async logic is running as fast as it can, it is going to have 2
to 3 times the power dissipated, as that is how many more wires and
transistors are switching. Asnyc when doing nothing is very low power.
I just love systems that do nothing: they end up going away (why does
anyone care what a system does when it has nothing to do? Just turn it
off!).

Their press announcement did say that now that they have the core
working, they need to get their (hardened?) IP to work, next.

Without all these bells and whistles that now make up a modern FPGA
offering, they are basically back in the XC2064 era: basic fabric, some
IO, and no tools.

One other point: their design is about 16X more area (less density)
than a modern FPGA. That is going to be a real killer - <100K gates for
~$10? When the market is at 1M+ gates for <$10?

Good luck.

Async design is a religion, and you either believe it will save you, or
you don't. I'm just a sceptic. I am still waiting to see it do
something useful in the marketplace.

More interesting (I think) is the (synchronous) FPOA, with its enforced
pipelining, and medium grain architecture aimed at extreme DSP
applications. At least that product looks like one can actually use it,
and it does something. Although 30W power dissipation is just about
twice what most folks can deal with.

Austin

dp wrote:

>>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply
>>range. 0.2V is not much voltage at all... I would have thought
>>transistor threshold voltages would have caused issues at such a low
>>voltage. How are they achieving such low threshold voltages?

>
>
> Sounds interesting to me as well, perhaps some of the other 90nm
> manufacturers could shed some light - does it really work? Probably
> not at full speed, but even at DC - do the FETs really turn on at 0.2
> V?
> While I am not sure what this synchronous/asynchronous gimmick is
> all about I would say I am glad they may soon have a marketable
> alternative to the rest of the makers, I guess they all became a bit
> too big to talk to (and stay innovative).
>
> Dimiter
>
> ------------------------------------------------------
> Dimiter Popoff Transgalactic Instruments
>
> http://www.tgi-sci.com
> ------------------------------------------------------
>
>
> Bevan Weiss wrote:
>
>>Jim Granville wrote:
>>
>>>For those interested in Async devices, and uses :
>>>
>>>http://www.achronix.com/news.html?ne...69ce9b919f7562
>>>
>>>
>>>It is a way's off being usable, but the numbers are impressive
>>>
>>> No mention of device size, but the info suggests they target the
>>>high-price/low volume user space.
>>> [ Not too many customers need -196'C ]
>>>
>>>.. and no mention of design tools, which may prove to be a bigger
>>>challenge than the silicon.
>>>
>>>-jg

>>
>>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply
>>range. 0.2V is not much voltage at all... I would have thought
>>transistor threshold voltages would have caused issues at such a low
>>voltage. How are they achieving such low threshold voltages?
>>
>>
>>Bevan

>
>

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  #7 (permalink)  
Old 04-26-2006, 05:39 PM
John_H
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Posts: n/a
Default Re: Async FPGA ~2GHz

"Jim Granville" <[email protected]> wrote in message
news:[email protected]
>
> I realise that, of course, - the comment still stands :
> Do you have an app that needs to go to -196'C ?
> Mars is the only deployment I can think of, most others are
> covered by the terrestrial Military -55'C - 125'C range.
>
> -jg


How cold does it get in space? (where no one can hear you scream)

They'd potentially have another market if the increased the operating
temperature well beyond 130'C - downhole applications in the oil industry,
for instance.


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  #8 (permalink)  
Old 04-26-2006, 06:38 PM
Guest
 
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Default Re: Async FPGA ~2GHz

>They'd potentially have another market if the increased the operating
>temperature well beyond 130'C - downhole applications in the oil industry,
>for instance.


How hot are those ..?

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  #9 (permalink)  
Old 04-26-2006, 07:39 PM
dp
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Default Re: Async FPGA ~2GHz

Austin,

thanks for the info. So 0.2V being > the treshold voltage is not
surprising at 90nm. I had no idea where the breakthrough voltage would
be, your mentioning the 3.9V makes me think it is about 5V. Not so
bad, come to think we are used to reverse base emitter voltage around
6-7V (and about 3 for some really hf parts) for decades.. :-).

> Without all these bells and whistles that now make up a modern FPGA
> offering, they are basically back in the XC2064 era: basic fabric, some
> IO, and no tools.


On a side note, what did Xilinx do back then? I doubt they have made
the specification of the insides public so other people could write
their
tools (I keep on dreaming abou that day....), what was it?

> One other point: their design is about 16X more area (less density)
> than a modern FPGA. That is going to be a real killer - <100K gates for
> ~$10? When the market is at 1M+ gates for <$10?


Well they appear to be targetting some (most likely speed) specs
which are much better than the rest and hope to get into busyness
based on that. If their specs are just, say, 1.something better, it
will
take more than that to stay alive - but if they are well connected they
might well get some big contract to give them the starting kick.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


Austin Lesea wrote:
> dp,
>
> Even Intel has realized that frequency kills. Not sure why they are so
> excited about touting 2 GHz.
>
> The fets are running in "active mode" basically just behaving as analog
> (low gain) transistor amplifiers in their sub threshold regions...kinda
> on, kinda off, kinda inbetween.
>
> I am sure that the speed of operation is very slow down at 0.2V.
>
> At 3.9 volts on a 90nm transistor, I am guessing the lifetime to
> breakdown is about a week, or sooner.
>
> I'd like to see them get block RAM, processors, DLL's/PLL's, MGTs, etc.
> to work in the same fashion. I am sure we all know the stories of the
> attempts at making async microprocessors, and how they were abandoned
> for having far too much area, and no real performance benefits.
>
> And when async logic is running as fast as it can, it is going to have 2
> to 3 times the power dissipated, as that is how many more wires and
> transistors are switching. Asnyc when doing nothing is very low power.
> I just love systems that do nothing: they end up going away (why does
> anyone care what a system does when it has nothing to do? Just turn it
> off!).
>
> Their press announcement did say that now that they have the core
> working, they need to get their (hardened?) IP to work, next.
>
> Without all these bells and whistles that now make up a modern FPGA
> offering, they are basically back in the XC2064 era: basic fabric, some
> IO, and no tools.
>
> One other point: their design is about 16X more area (less density)
> than a modern FPGA. That is going to be a real killer - <100K gates for
> ~$10? When the market is at 1M+ gates for <$10?
>
> Good luck.
>
> Async design is a religion, and you either believe it will save you, or
> you don't. I'm just a sceptic. I am still waiting to see it do
> something useful in the marketplace.
>
> More interesting (I think) is the (synchronous) FPOA, with its enforced
> pipelining, and medium grain architecture aimed at extreme DSP
> applications. At least that product looks like one can actually use it,
> and it does something. Although 30W power dissipation is just about
> twice what most folks can deal with.
>
> Austin
>
> dp wrote:
>
> >>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply
> >>range. 0.2V is not much voltage at all... I would have thought
> >>transistor threshold voltages would have caused issues at such a low
> >>voltage. How are they achieving such low threshold voltages?

> >
> >
> > Sounds interesting to me as well, perhaps some of the other 90nm
> > manufacturers could shed some light - does it really work? Probably
> > not at full speed, but even at DC - do the FETs really turn on at 0.2
> > V?
> > While I am not sure what this synchronous/asynchronous gimmick is
> > all about I would say I am glad they may soon have a marketable
> > alternative to the rest of the makers, I guess they all became a bit
> > too big to talk to (and stay innovative).
> >
> > Dimiter
> >
> > ------------------------------------------------------
> > Dimiter Popoff Transgalactic Instruments
> >
> > http://www.tgi-sci.com
> > ------------------------------------------------------
> >
> >
> > Bevan Weiss wrote:
> >
> >>Jim Granville wrote:
> >>
> >>>For those interested in Async devices, and uses :
> >>>
> >>>http://www.achronix.com/news.html?ne...69ce9b919f7562
> >>>
> >>>
> >>>It is a way's off being usable, but the numbers are impressive
> >>>
> >>> No mention of device size, but the info suggests they target the
> >>>high-price/low volume user space.
> >>> [ Not too many customers need -196'C ]
> >>>
> >>>.. and no mention of design tools, which may prove to be a bigger
> >>>challenge than the silicon.
> >>>
> >>>-jg
> >>
> >>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply
> >>range. 0.2V is not much voltage at all... I would have thought
> >>transistor threshold voltages would have caused issues at such a low
> >>voltage. How are they achieving such low threshold voltages?
> >>
> >>
> >>Bevan

> >
> >


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  #10 (permalink)  
Old 04-26-2006, 07:53 PM
Bob Perlman
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Posts: n/a
Default Re: Async FPGA ~2GHz

On Wed, 26 Apr 2006 16:24:21 +1200, Jim Granville
<[email protected]> wrote:

>stuff on new asynch. FPGA announcement skipped
>
>.. and no mention of design tools, which may prove to be a bigger
>challenge than the silicon.


Truer words were never spoken.

Bob Perlman
Cambrian Design Works
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  #11 (permalink)  
Old 04-26-2006, 08:14 PM
John_H
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Posts: n/a
Default Re: Async FPGA ~2GHz

<[email protected]> wrote in message
news:[email protected]
> >They'd potentially have another market if the increased the operating
>>temperature well beyond 130'C - downhole applications in the oil industry,
>>for instance.

>
> How hot are those ..?


From one of Peter Alfke's posts here (May 15th, 2003):

"Silicon is one tough material ! The 125 or even 150 degree limit is
more a plastic package issue than a silicon issue. I have helped
down-hole (oil-drilling) applications where our chips functioned (with
relaxed performance) for many weeks at 175 degree ambient, and the user
was pushing for 200 degrees."


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  #12 (permalink)  
Old 04-26-2006, 08:25 PM
Guest
 
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Default Re: Async FPGA ~2GHz


Austin Lesea wrote:
> I am sure we all know the stories of the
> attempts at making async microprocessors, and how they were abandoned
> for having far too much area, and no real performance benefits.


The jury is still out on that one, as we noted a couple months back
with the ARM.

> And when async logic is running as fast as it can, it is going to have 2
> to 3 times the power dissipated, as that is how many more wires and
> transistors are switching.


Actually, when you count the clock in a sync design based on lut/ff it
works out about the same, especially when you include the clock
distribution network.

> Asnyc when doing nothing is very low power.
> I just love systems that do nothing: they end up going away (why does
> anyone care what a system does when it has nothing to do? Just turn it
> off!).


I don't see that being any different that having to leave half an FPGA
idle when you need to turn up the frequency on your FPGA's because of
heat/power limits.

> One other point: their design is about 16X more area (less density)
> than a modern FPGA. That is going to be a real killer - <100K gates for
> ~$10? When the market is at 1M+ gates for <$10?


Seems that you have said a number of times that the wasted area in an
FPGA as compared to ASIC wasn't a problem????

> Async design is a religion, and you either believe it will save you, or
> you don't.


hardly. More like it solves your problems or not.

> Although 30W power dissipation is just about
> twice what most folks can deal with.


Yep ... even with your parts.

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  #13 (permalink)  
Old 04-26-2006, 08:45 PM
Jim Granville
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Posts: n/a
Default Re: Async FPGA ~2GHz

dp wrote:
>>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply
>>range. 0.2V is not much voltage at all... I would have thought
>>transistor threshold voltages would have caused issues at such a low
>>voltage. How are they achieving such low threshold voltages?

>
>
> Sounds interesting to me as well, perhaps some of the other 90nm
> manufacturers could shed some light - does it really work? Probably
> not at full speed, but even at DC - do the FETs really turn on at 0.2
> V?


Note they were carefull in the wording : "operated correctly".

I would place 0.2V at a data-retention point, not a clocking one.

CMOS nodes will 'stay-put' at much lower voltages than they will toggle,
and there is a clear need for a spec point that allows instant-config
from the lowest possible Icc.

Xilinx have been playing a little with this, but so far are a long way
off 0.2V

-jg


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  #14 (permalink)  
Old 04-26-2006, 09:02 PM
Austin Lesea
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Posts: n/a
Default Re: Async FPGA ~2GHz

dp,

Some comments,

Austin

-snip-

> thanks for the info. So 0.2V being > the treshold voltage is not
> surprising at 90nm. I had no idea where the breakthrough voltage would
> be


The Vt is defined as the voltage at which the Idsat is X. The
transistor has a subthreshold region where some voltage causes some
current to flow, well down to the millivolts. It isn't digital at all.
It is all analog design...

, your mentioning the 3.9V makes me think it is about 5V. Not so
> bad, come to think we are used to reverse base emitter voltage around
> 6-7V (and about 3 for some really hf parts) for decades.. :-).


You would blow the 90nm gate to smithereens in a blink at 6 volts.

-snip-
> On a side note, what did Xilinx do back then? I doubt they have made
> the specification of the insides public so other people could write
> their
> tools (I keep on dreaming abou that day....), what was it?


No, we made our own crude (really) tools, and folks made use of them,
and folks started to ask us for better ones, and slowly we figured out
how, and provided better and better tools.

No one was interested in making tools for some unknown and unheard of
company that was "wasting" transistors. Back then, we were vilified by
the semi industry as being quacks, and con artists (almost).

Real semi companies owned their own fab, and carved their own masks on
rubylith with Xacto knives.

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  #15 (permalink)  
Old 04-26-2006, 09:03 PM
Austin Lesea
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Posts: n/a
Default Re: Async FPGA ~2GHz

fpga_toys,

Only comment is that the async FPGA is 16X our area. Not 16X the area
of an asic designed to do the same job.

Austin

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  #16 (permalink)  
Old 04-26-2006, 09:06 PM
Jim Granville
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Posts: n/a
Default Re: Async FPGA ~2GHz

Austin Lesea wrote:

> dp,
>
> One other point: their design is about 16X more area (less density)
> than a modern FPGA.


That number comes from where ?

> That is going to be a real killer - <100K gates for
> ~$10? When the market is at 1M+ gates for <$10?


Let's stand back a little, and consider markets :

Pure Logic is still a > $2B business, and the ECL/LVDS sides of that
are not going away, but are increasing.

Sometimes pure MHz really does matter, and price is secondary.

Will this replace the vanilla FPGAs = no.
Could one of these sit alongside a vanilla FPGA ( just like
ECL and LVDS blocks do right now ) = yes.


Taking an even wider perspective, it pays to remember the ASIC market is
still much higher $$$ than FPGAs - in dollar terms, FPGAs are a fringe
business, and in pure performance, they also struggle.
- but that still leaves enough customers to support a $2-3B FPGA sector


> Good luck.


I think there is plenty of room for them.
Xilinx might even buy them out, in 2007....

-jg


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  #17 (permalink)  
Old 04-26-2006, 09:16 PM
Guest
 
Posts: n/a
Default Re: Async FPGA ~2GHz


Jim Granville wrote:
> I think there is plenty of room for them.
> Xilinx might even buy them out, in 2007....


Or maybe Altera will and port C2H to it

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  #18 (permalink)  
Old 04-26-2006, 09:31 PM
Austin Lesea
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Posts: n/a
Default Re: Async FPGA ~2GHz

jg,

Who knows?

The estimates come from earlier papers that were published by this group
when they were students and professors before they found funding.

Who knows? They don't have anything but slick press releases right now.

Plenty of room for specialty stuff in the market. Just have to pick the
right stuff.

Is the extreme DSP market 2B$? 5B$ Or is it 500M$? Who is going after
it? All part of the game.

Is it like the structured ASIC market? All hot air, and no money (with
folks leaving so fast)?

How does the cost of the next process ASIC affect their business model?

Can they hope to layout in 65nm and release that in 2008 when we are at
full production with 65nm -- 65nm will be the 'old' product then? We
will beat them on processing power by just being ahead a node or two.

Got to think about that business model: they can use up all that seed
money pretty fast fixing masks....only to face a 35nm FPGA that is 1/8
the cost and area, and 4X the performance?

And their claims of space, radiation, etc. means they have to use
epitaxial wafers (not bulk CMOS), and they have to be heavy ion immune
to latchup, SEL, SEU, SER, etc....that is a much tougher thing to prove!

Our QPRO line is already in space, and does work. Has a history of
success. Space folks are real hard to convince to do anything new
(believe me, I have tried). No one wants their mission to be the one
that is used as the "case study of a disaster."

Austin

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  #19 (permalink)  
Old 04-26-2006, 09:36 PM
Peter Alfke
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Default Re: Async FPGA ~2GHz

If I worked for a company that has nothing available to sell, I would
really be embarrased if somebody forced me to brag about multi-million
gates and 1.93 GHz in one paragraph, and minus 196 degree operation,
and 0.2 V to 3.9 V supply voltage in the next.
But normally super-critical people that enjoy nailing us for the
slightest oversight, just drool...
The date was April 24, maybe it was just 23 days delayed...
Peter Alfke, speaking for himself

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  #20 (permalink)  
Old 04-26-2006, 09:46 PM
Guest
 
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Default Re: Async FPGA ~2GHz


Austin Lesea wrote:
> Only comment is that the async FPGA is 16X our area. Not 16X the area
> of an asic designed to do the same job.


No question. The point is that is their first silicon cut, will likely
get smaller over time, and that as you have clearly said in the past
that die size isn't everything, but rather it's the cost/performance of
the finished product. So your argument why the bloated size of an FPGA
in comparision to ASIC equally applies to other products as well --
it's the end customer, not their competitors, that decides if the
product has reasonable cost/performance to design their products with.

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  #21 (permalink)  
Old 04-26-2006, 09:52 PM
Guest
 
Posts: n/a
Default Re: Async FPGA ~2GHz


Peter Alfke wrote:
> If I worked for a company that has nothing available to sell, I would
> really be embarrased if somebody forced me to brag about multi-million
> gates and 1.93 GHz in one paragraph, and minus 196 degree operation,
> and 0.2 V to 3.9 V supply voltage in the next.


Is that how Xilinx enginering and sales feels when they are out pumping
interest in next generation product (before finished production parts
are available) with select customers looking for advanced design wins?

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  #22 (permalink)  
Old 04-26-2006, 10:47 PM
Eric Smith
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Default Re: Async FPGA ~2GHz

Peter Alfke wrote:
> If I worked for a company that has nothing available to sell, I would
> really be embarrased if somebody forced me to brag about multi-million
> gates and 1.93 GHz in one paragraph, and minus 196 degree operation,
> and 0.2 V to 3.9 V supply voltage in the next.


[email protected] writes:
> Is that how Xilinx enginering and sales feels when they are out pumping
> interest in next generation product (before finished production parts
> are available) with select customers looking for advanced design wins?


It's how any reasonable engineer feels looking at those ridiculous
claims. Don't tell me you believe them?
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  #23 (permalink)  
Old 04-26-2006, 10:47 PM
dp
Guest
 
Posts: n/a
Default Re: Async FPGA ~2GHz

Austin,

some more from me,

> The Vt is defined as the voltage at which the Idsat is X. ...


I was referring to the voltage below which the channel is off,
i.e. the cutoff voltage, so we are talking about the same thing.
I have extensive experience using FETs in analog designs
(mostly JFETs, of course), but I may well have forgotten
which letter goes for which parameter. Of course I know you
won't open a FET down to its lowest achievable Rdson at 2GHz
(I believe this is what you refer to as "saturation").

> You would blow the 90nm gate to smithereens in a blink at 6 volts.


Yep, apparently so, what I noted to myself was that they could
survive (sometimes perhaps not) a short term 3.3V glitch (not that
I would like to do it but with all these multiple supply voltages
nowadays one just cannot avoid the thought... :-).

> No one was interested in making tools for some unknown and unheard of
> company that was "wasting" transistors. Back then, we were vilified by
> the semi industry as being quacks, and con artists (almost).


This must have been in the pre-LCA time, back in 1990 or so I asked
about the programming specs of the LCA and was denied it. I did
appreciate the devices then, I still do now, my only problem is that
all my design tools are under my control (this gives a world of a
difference so many times). Well, the truth is, I have never gone
hard enough after the FPGA data, so I don't really know how
difficult to achieve this goal is. Some time ago I got some valuable
help from Peter on other devices I use, I imagine if I really
need something and (as it happens to be) I am not in anyone's
way things could be sorted out...

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------




Austin Lesea wrote:
> dp,
>
> Some comments,
>
> Austin
>
> -snip-
>
> > thanks for the info. So 0.2V being > the treshold voltage is not
> > surprising at 90nm. I had no idea where the breakthrough voltage would
> > be

>
> The Vt is defined as the voltage at which the Idsat is X. The
> transistor has a subthreshold region where some voltage causes some
> current to flow, well down to the millivolts. It isn't digital at all.
> It is all analog design...
>
> , your mentioning the 3.9V makes me think it is about 5V. Not so
> > bad, come to think we are used to reverse base emitter voltage around
> > 6-7V (and about 3 for some really hf parts) for decades.. :-).

>
> You would blow the 90nm gate to smithereens in a blink at 6 volts.
>
> -snip-
> > On a side note, what did Xilinx do back then? I doubt they have made
> > the specification of the insides public so other people could write
> > their
> > tools (I keep on dreaming abou that day....), what was it?

>
> No, we made our own crude (really) tools, and folks made use of them,
> and folks started to ask us for better ones, and slowly we figured out
> how, and provided better and better tools.
>
> No one was interested in making tools for some unknown and unheard of
> company that was "wasting" transistors. Back then, we were vilified by
> the semi industry as being quacks, and con artists (almost).
>
> Real semi companies owned their own fab, and carved their own masks on
> rubylith with Xacto knives.


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  #24 (permalink)  
Old 04-26-2006, 10:58 PM
Guest
 
Posts: n/a
Default Re: Async FPGA ~2GHz


Austin Lesea wrote:
> jg,
>
> Who knows?
>
> The estimates come from earlier papers that were published by this group
> when they were students and professors before they found funding.
>
> Who knows? They don't have anything but slick press releases right now.


Having spent most the 1980's and 1990's working with early startups,
there is another factor that you seem to miss. Startups are frequently
captive design/production facilities to larger companies that need that
product, and greatly influence the intial product design by stating
what they want to buy. When a large early customer says "I need x, y,
and z delivered in 100K qty" between two dates, that becomes your
product, business plan, and production schedule.

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  #25 (permalink)  
Old 04-26-2006, 11:01 PM
Guest
 
Posts: n/a
Default Re: Async FPGA ~2GHz


Eric Smith wrote:
> It's how any reasonable engineer feels looking at those ridiculous
> claims. Don't tell me you believe them?


It's not a mater of belief, they will either deliver or not. In 35
years of engineering I've done my share of products that people said
can not be done, and delivered to their disbelief.

We have modems today that broke the modulation "laws" set in 60's ...
by more than an order of magnitude. We have semi design rules today,
that exceeded a large number of "walls" in process over the last 30
years too. There are many more examples of what can not be done, that
have be easily broken by innovative engineers.

So, I'm not in a big hurry to claim what can not be done ... I'll wait
and see what is delivered, rather than ranting about what is impossble.

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