FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-28-2006, 07:21 AM
billu
Guest
 
Posts: n/a
Default Assigning MGT's in sample Aurora Design

Hi There,

I just generated a Aurora sample design that communicates between 2
MGT's using Coregenerator. How do I configure two specific MGT's to be
used in the design (say MGT4 & MGT9). I tried to use PACE to assign
I/O's of the Aurora design to the pins on the board. But, the MGT pins
are disabled. (color coded:Brown and the legend:Gigabit serial) How do
I assign the assign the TX signals (TX_N & TX_P) and RX (RX_N & RX_P)
to the MGTs?

Thx in advance,
Billu

Reply With Quote
  #2 (permalink)  
Old 04-28-2006, 09:00 AM
colin
Guest
 
Posts: n/a
Default Re: Assigning MGT's in sample Aurora Design


billu wrote:
> Hi There,
>
> I just generated a Aurora sample design that communicates between 2
> MGT's using Coregenerator. How do I configure two specific MGT's to be
> used in the design (say MGT4 & MGT9). I tried to use PACE to assign
> I/O's of the Aurora design to the pins on the board. But, the MGT pins
> are disabled. (color coded:Brown and the legend:Gigabit serial) How do
> I assign the assign the TX signals (TX_N & TX_P) and RX (RX_N & RX_P)
> to the MGTs?
>
> Thx in advance,
> Billu


Haven't used it for about a year but as I recall, the coregen gui
controls some of it and you modify the ucf which coregen generates to
do the rest.

Colin

Reply With Quote
  #3 (permalink)  
Old 04-28-2006, 09:12 AM
sjulhes
Guest
 
Posts: n/a
Default Re: Assigning MGT's in sample Aurora Design

Last time I used it, you had to choose the MGT you want among all the
proposed ones ( depending on you FPGA ) by the core generator.
The generation of the IP by core generator fills a ucf file for you.
Just include the generated ucf content to your design ucf file.



"billu" <[email protected]> a écrit dans le message de news:
[email protected] com...
> Hi There,
>
> I just generated a Aurora sample design that communicates between 2
> MGT's using Coregenerator. How do I configure two specific MGT's to be
> used in the design (say MGT4 & MGT9). I tried to use PACE to assign
> I/O's of the Aurora design to the pins on the board. But, the MGT pins
> are disabled. (color coded:Brown and the legend:Gigabit serial) How do
> I assign the assign the TX signals (TX_N & TX_P) and RX (RX_N & RX_P)
> to the MGTs?
>
> Thx in advance,
> Billu
>



Reply With Quote
  #4 (permalink)  
Old 04-28-2006, 03:35 PM
Paul Hartke
Guest
 
Posts: n/a
Default Re: Assigning MGT's in sample Aurora Design

The actual MGT pins are completely determined by the MGT location from
the ucf:
"INST aurora_module_i_1/lane_0_mgt_i LOC=GT_X0Y1;"

You can specify this location in the Coregen GUI as another poster
mentioned or simply edit the ucf afterwards like the "Using High Speed
Serial MGTs with the Aurora IP" at
http://www.xilinx.com/univ/xupv2p.html does.

Don't forget to change any other per MGT constraints such as the "Phase
Align Module" LOC.

Paul

billu wrote:
>
> Hi There,
>
> I just generated a Aurora sample design that communicates between 2
> MGT's using Coregenerator. How do I configure two specific MGT's to be
> used in the design (say MGT4 & MGT9). I tried to use PACE to assign
> I/O's of the Aurora design to the pins on the board. But, the MGT pins
> are disabled. (color coded:Brown and the legend:Gigabit serial) How do
> I assign the assign the TX signals (TX_N & TX_P) and RX (RX_N & RX_P)
> to the MGTs?
>
> Thx in advance,
> Billu

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Testing sample Aurora design on ML321 board billu FPGA 9 04-18-2006 07:41 PM
FPGA design sample for Compact Flash peripheral Johnson FPGA 2 11-29-2004 06:50 PM
Xilinx 804 Aurora vhdl Design patch Jeremie Veyret FPGA 3 08-17-2004 06:37 PM
Question regarding the sample design in XAPP290. Kelvin, Chee FPGA 0 12-25-2003 03:34 PM


All times are GMT +1. The time now is 06:51 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved