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Old 04-11-2006, 05:27 AM
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Default Area Constraints in Xilinx

Hi,
Im somewhat new to the ISE and was wondering if there was a way to
give the Xilinx tool an area constraint ( say in number of LUT's used)
for a given VHDL implementation? For instance, I have created a module
that I want to restrict to 500 LUT's if possible, because I will be
having other modules that will need the pending space. Im not exactly
sure how I would go about this using the PACE tool, and any help would
be appreciated. I am sure there is a trivial way to do it, but I seem
to be overlooking it at the moment

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Old 04-11-2006, 04:50 PM
John_H
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Default Re: Area Constraints in Xilinx

<[email protected]> wrote in message
news:[email protected] oups.com...
> Hi,
> Im somewhat new to the ISE and was wondering if there was a way to
> give the Xilinx tool an area constraint ( say in number of LUT's used)
> for a given VHDL implementation? For instance, I have created a module
> that I want to restrict to 500 LUT's if possible, because I will be
> having other modules that will need the pending space. Im not exactly
> sure how I would go about this using the PACE tool, and any help would
> be appreciated. I am sure there is a trivial way to do it, but I seem
> to be overlooking it at the moment


Check out the AREA GROUP constraint in the online software manual.
You can associate the module with a group and provide a range for elements
in that group.


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