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Old 07-21-2004, 01:11 AM
Ramtilak
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Default Area constraint on a sub-module

Hi,

Can anyone suggest how to assign a area constraint on a sub-module
within my design? I dont care where the other sub-modules are as long
as this particular sub-module is in the required area. I know we can
assign a area constraint for the whole design. But, how to do it for a
sub-module?

Thanks in advance,
Ramtilak
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  #2 (permalink)  
Old 07-21-2004, 03:16 AM
Jim Wu
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Default Re: Area constraint on a sub-module



Ramtilak wrote:
> Hi,
>
> Can anyone suggest how to assign a area constraint on a sub-module
> within my design? I dont care where the other sub-modules are as long
> as this particular sub-module is in the required area. I know we can
> assign a area constraint for the whole design. But, how to do it for a
> sub-module?


For Xilinx FPGA and tools, add something like below to the ucf file:

INST “hierarchy/path/to/submodule” AREA_GROUP = "your_area_group_name";
AREA_GROUP “your_area_group_name” RANGE = range;

HTH,
Jim ([email protected] remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips
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  #3 (permalink)  
Old 07-21-2004, 04:13 AM
Cody
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Default Re: Area constraint on a sub-module

remember to check the KEEP_HIERARCHY in the XST Options, and put
AREA_GROUP “your_area_group_name” PLACE = CLOSED;
AREA_GROUP “your_area_group_name” GROUP = CLOSED;

Kelvin





"Jim Wu" <[email protected]> wrote in message
news:[email protected]
>
>
> Ramtilak wrote:
> > Hi,
> >
> > Can anyone suggest how to assign a area constraint on a sub-module
> > within my design? I dont care where the other sub-modules are as long
> > as this particular sub-module is in the required area. I know we can
> > assign a area constraint for the whole design. But, how to do it for a
> > sub-module?

>
> For Xilinx FPGA and tools, add something like below to the ucf file:
>
> INST “hierarchy/path/to/submodule” AREA_GROUP = "your_area_group_name";
> AREA_GROUP “your_area_group_name” RANGE = range;
>
> HTH,
> Jim ([email protected] remve NOOOSPAM)
> http://www.geocities.com/jimwu88/chips



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  #4 (permalink)  
Old 07-22-2004, 12:01 PM
Yttrium
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Posts: n/a
Default Re: Area constraint on a sub-module

or you could use the incremental design flow

http://toolbox.xilinx.com/docsan/xil...xst0035_6.html

"Cody" <[email protected]> wrote in message
news:[email protected]
> remember to check the KEEP_HIERARCHY in the XST Options, and put
> AREA_GROUP "your_area_group_name" PLACE = CLOSED;
> AREA_GROUP "your_area_group_name" GROUP = CLOSED;
>
> Kelvin
>
>
>
>
>
> "Jim Wu" <[email protected]> wrote in message
> news:[email protected]
> >
> >
> > Ramtilak wrote:
> > > Hi,
> > >
> > > Can anyone suggest how to assign a area constraint on a sub-module
> > > within my design? I dont care where the other sub-modules are as long
> > > as this particular sub-module is in the required area. I know we can
> > > assign a area constraint for the whole design. But, how to do it for a
> > > sub-module?

> >
> > For Xilinx FPGA and tools, add something like below to the ucf file:
> >
> > INST "hierarchy/path/to/submodule" AREA_GROUP = "your_area_group_name";
> > AREA_GROUP "your_area_group_name" RANGE = range;
> >
> > HTH,
> > Jim ([email protected] remve NOOOSPAM)
> > http://www.geocities.com/jimwu88/chips

>
>



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