Hi,
I have big problem to move my project (NIOS + some hardware) from
CYCLONE to APEX20K200. During fit, I have masg:
Error: Logic cell ref_16_system:inst|cpu:the_cpu|cpu_pipeline:the_cp u_pipeline|cpu_compact_alu:the_cpu_compact_alu|cpu _adder_logic_lock_region:the_cpu_adder_logic_lock_ region|cpu_aluadder:the_cpu_aluadder|cpu_hidden_lc ell_4CEF:carryout_reg|regout
requires 5 secondary signals of types non-global clock, non-global
clock enable, non-global clear, non-global synchronous clear, and
non-global synchronous load, but the selected device allows only 4
signals
Quartus HELP remarks, that I have to switch Auto Global Clock and
Signals "ON". I did it, but error still keep. What I can do?
Best regards
Leszek
[email protected]