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  #1 (permalink)  
Old 11-01-2007, 06:26 PM
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Default Another way to handle floating inputs.

Has anyone implemented a circuit similar to the one below?

VCC
+
|
.---------------o
| |
| |
| .-.
| | |
| | | weak pullup
| '-'
| |
| |
| .-----o
| | | -----
| |\| | | |
--------| >-----|-------| PIN |
|/ | | |
| -----
|
| floating
| or
| GND
/| |
To Internal Fpga Logic <---------< |-------
\|
(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)


When the input pin is floating, the weak pullup causes the output
buffer to drive Vcc out, negating any extraneous noise that may exist
on the external line.

When the input pin is driven to ground, the buffer momentarily tries
driving Vcc to ground but stops once the tristate is disabled.

I've always just used a weak pullup on the input (no tristate buffer
at all) but another engineer in our group says this is a good way to
protect input pins from noise on undriven inputs. I'm a little
concerned about the brief period of time when the tristate buffer is
driving ground but he assures me that the fpga can handle it.

Do you agree?

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  #2 (permalink)  
Old 11-01-2007, 07:25 PM
austin
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Default Re: Another way to handle floating inputs.

Petrov,

Why are you trying to do this?

What is it supposed to protect the FPGA from?

Austin
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  #3 (permalink)  
Old 11-01-2007, 07:50 PM
Jim Granville
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Posts: n/a
Default Re: Another way to handle floating inputs.

[email protected] wrote:

> Has anyone implemented a circuit similar to the one below?
>
> VCC
> +
> |
> .---------------o
> | |
> | |
> | .-.
> | | |
> | | | weak pullup
> | '-'
> | |
> | |
> | .-----o
> | | | -----
> | |\| | | |
> --------| >-----|-------| PIN |
> |/ | | |
> | -----
> |
> | floating
> | or
> | GND
> /| |
> To Internal Fpga Logic <---------< |-------
> \|
> (created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)
>
>
> When the input pin is floating, the weak pullup causes the output
> buffer to drive Vcc out, negating any extraneous noise that may exist
> on the external line.
>
> When the input pin is driven to ground, the buffer momentarily tries
> driving Vcc to ground but stops once the tristate is disabled.
>
> I've always just used a weak pullup on the input (no tristate buffer
> at all) but another engineer in our group says this is a good way to
> protect input pins from noise on undriven inputs.


Wow - How much noise is he used to dealing with ?

> I'm a little
> concerned about the brief period of time when the tristate buffer is
> driving ground but he assures me that the fpga can handle it.


Also be worried about if the contention can get past the logic threshold.

>
> Do you agree?


Yes, "the fpga can handle it" - but you have wider issues.
Can the device driving the fPGA handle it.
You would need to spec the lowest drive option on the FPGA,
and the best drive on the external device.
What if the designer of the external device is thinking exactly the same
as you

The 80C51 has a port structure similar, but they use Weak PFET and
Strong NFET, so they know they will not get stuck in no-mans land with
part variations.

-jg



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  #4 (permalink)  
Old 11-01-2007, 07:50 PM
Guest
 
Posts: n/a
Default Re: Another way to handle floating inputs.

On Nov 1, 2:25 pm, austin <[email protected]> wrote:
> Petrov,
>
> Why are you trying to do this?
>
> What is it supposed to protect the FPGA from?
>
> Austin


I'm not convinced I should be trying this, that's the problem. I've
always just enabled a weak pullup resistor on the input of a floating
pin. My coworker is trying to convince me that this approach offers
better noise immunity when nothing is connected to the input pin.

The thing is, this input feeds a two-stage synchronizer... I would
think that alone would eliminate most noise to the synchronous logic
that follows.


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  #5 (permalink)  
Old 11-01-2007, 07:52 PM
Guest
 
Posts: n/a
Default Re: Another way to handle floating inputs.

On Nov 1, 2:50 pm, Jim Granville <[email protected]>
wrote:
> [email protected] wrote:
> > Has anyone implemented a circuit similar to the one below?

>
> > VCC
> > +
> > |
> > .---------------o
> > | |
> > | |
> > | .-.
> > | | |
> > | | | weak pullup
> > | '-'
> > | |
> > | |
> > | .-----o
> > | | | -----
> > | |\| | | |
> > --------| >-----|-------| PIN |
> > |/ | | |
> > | -----
> > |
> > | floating
> > | or
> > | GND
> > /| |
> > To Internal Fpga Logic <---------< |-------
> > \|
> > (created by AACircuit v1.28.6 beta 04/19/05www.tech-chat.de)

>
> > When the input pin is floating, the weak pullup causes the output
> > buffer to drive Vcc out, negating any extraneous noise that may exist
> > on the external line.

>
> > When the input pin is driven to ground, the buffer momentarily tries
> > driving Vcc to ground but stops once the tristate is disabled.

>
> > I've always just used a weak pullup on the input (no tristate buffer
> > at all) but another engineer in our group says this is a good way to
> > protect input pins from noise on undriven inputs.

>
> Wow - How much noise is he used to dealing with ?
>
> > I'm a little
> > concerned about the brief period of time when the tristate buffer is
> > driving ground but he assures me that the fpga can handle it.

>
> Also be worried about if the contention can get past the logic threshold.
>
>
>
> > Do you agree?

>
> Yes, "the fpga can handle it" - but you have wider issues.
> Can the device driving the fPGA handle it.
> You would need to spec the lowest drive option on the FPGA,
> and the best drive on the external device.
> What if the designer of the external device is thinking exactly the same
> as you
>
> The 80C51 has a port structure similar, but they use Weak PFET and
> Strong NFET, so they know they will not get stuck in no-mans land with
> part variations.
>
> -jg- Hide quoted text -
>
> - Show quoted text -


My coworker did suggest setting the drive to the lowest setting. I
assume he's done this on past designs... I've just never seen it
before.

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  #6 (permalink)  
Old 11-01-2007, 07:55 PM
Dave Pollum
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Posts: n/a
Default Re: Another way to handle floating inputs.

On Nov 1, 1:50 pm, [email protected] wrote:
> On Nov 1, 2:25 pm, austin <[email protected]> wrote:
>
> > Petrov,

>
> > Why are you trying to do this?

>
> > What is it supposed to protect the FPGA from?

>
> > Austin

>
> I'm not convinced I should be trying this, that's the problem. I've
> always just enabled a weak pullup resistor on the input of a floating
> pin. My coworker is trying to convince me that this approach offers
> better noise immunity when nothing is connected to the input pin.
>
> The thing is, this input feeds a two-stage synchronizer... I would
> think that alone would eliminate most noise to the synchronous logic
> that follows.


So are you saying that the input to your synchronizer would be
floating???
-Dave Pollum

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  #7 (permalink)  
Old 11-01-2007, 08:01 PM
Guest
 
Posts: n/a
Default Re: Another way to handle floating inputs.

On Nov 1, 2:55 pm, Dave Pollum <[email protected]> wrote:
> On Nov 1, 1:50 pm, [email protected] wrote:
>
>
>
>
>
> > On Nov 1, 2:25 pm, austin <[email protected]> wrote:

>
> > > Petrov,

>
> > > Why are you trying to do this?

>
> > > What is it supposed to protect the FPGA from?

>
> > > Austin

>
> > I'm not convinced I should be trying this, that's the problem. I've
> > always just enabled a weak pullup resistor on the input of a floating
> > pin. My coworker is trying to convince me that this approach offers
> > better noise immunity when nothing is connected to the input pin.

>
> > The thing is, this input feeds a two-stage synchronizer... I would
> > think that alone would eliminate most noise to the synchronous logic
> > that follows.

>
> So are you saying that the input to your synchronizer would be
> floating???
> -Dave Pollum- Hide quoted text -
>
> - Show quoted text -


No... it would still have the weak pullup enabled.

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  #8 (permalink)  
Old 11-01-2007, 08:56 PM
austin
Guest
 
Posts: n/a
Default Re: Another way to handle floating inputs.

Petrov,

I can see no reason to do what your co-worker is suggesting, unless
there are IOs very near this input, and those IOs are switching with
large, and strong, currents (like LVCMOS 24 mA FAST, or PCI bus).

The above assumes that this input is only weakly driven. If there is a
strong driver to this input, then the only concern is if there is so
much cross-talk or bounce that a driven signal to this pin is upset
(requires many tens of mA of coupling, or volts of bounce!).

If there are nearby switching, and the concern is crosstalk or ground
bounce, then the real solution is to do the simulations, and either use
the right part (like the V4 or V5 with the SpaseChevron(tm) package
which minimizes crosstalk and bounce by a factor of 7.5 over other
solutions), or ground the pins on either side of the input (which is
another way to limit the crosstalk and bounce on the sensitive pin).

Your friend's idea may not harm the output (it will not), but it won't
really do what you want, either (deal with crosstalk or bounce).

Austin
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  #9 (permalink)  
Old 11-01-2007, 10:52 PM
Peter Alfke
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Posts: n/a
Default Re: Another way to handle floating inputs.


Similar structures can be used for contact de-bouncing.
Use a single-pole double-throw switch, connect the two poles to Vcc
and ground, and the moving arm to the FPGA input/output.
When input senses a Low, make the output drive low. When the input
senses High, make the output drive High.
The switch easily overrides the output driver (make it weak), and the
current spike lasts only a few nanoseconds. Doesn't work with a single-
throw switch...
Peter Alfke


On Nov 1, 10:26 am, [email protected] wrote:
> Has anyone implemented a circuit similar to the one below?
>
> VCC
> +
> |
> .---------------o
> | |
> | |
> | .-.
> | | |
> | | | weak pullup
> | '-'
> | |
> | |
> | .-----o
> | | | -----
> | |\| | | |
> --------| >-----|-------| PIN |
> |/ | | |
> | -----
> |
> | floating
> | or
> | GND
> /| |
> To Internal Fpga Logic <---------< |-------
> \|
> (created by AACircuit v1.28.6 beta 04/19/05www.tech-chat.de)
>
> When the input pin is floating, the weak pullup causes the output
> buffer to drive Vcc out, negating any extraneous noise that may exist
> on the external line.
>
> When the input pin is driven to ground, the buffer momentarily tries
> driving Vcc to ground but stops once the tristate is disabled.
>
> I've always just used a weak pullup on the input (no tristate buffer
> at all) but another engineer in our group says this is a good way to
> protect input pins from noise on undriven inputs. I'm a little
> concerned about the brief period of time when the tristate buffer is
> driving ground but he assures me that the fpga can handle it.
>
> Do you agree?



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  #10 (permalink)  
Old 11-02-2007, 11:10 AM
RCIngham
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Posts: n/a
Default Re: Another way to handle floating inputs.

This looks like "voodoo design" to me.
See http://foldoc.org/?voodoo+programming for the software equivalent.

If you know what the problem really is, design for that. Use series o
parallel termination to mitigate ground-bounce, for instance.

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  #11 (permalink)  
Old 11-02-2007, 04:56 PM
Peter Alfke
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Posts: n/a
Default Re: Another way to handle floating inputs.

Be specific. What do you mean by "this" ? Your posting is #10 in a
thread...
Peter Alfke

On Nov 2, 3:10 am, "RCIngham" <[email protected]> wrote:
> This looks like "voodoo design" to me.
> Seehttp://foldoc.org/?voodoo+programmingfor the software equivalent.
>
> If you know what the problem really is, design for that. Use series or
> parallel termination to mitigate ground-bounce, for instance.



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  #12 (permalink)  
Old 11-02-2007, 07:04 PM
comp.arch.fpga
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Posts: n/a
Default Re: Another way to handle floating inputs.

Why not use a weak keeper instead?
Older Xilinx part used that internally on tristate lines. You have a
weak buffer that drives the line to the voltage seen on the line.
An undriven line will quickly be driven to either 1 or 0 due to
initial noise. Another circuit driving the line will need to overcome
the keeper current (similar to a switching sram cell). The upside is:
There is no static current (unlike the pullup resistor).

Kolja Sulimma

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  #13 (permalink)  
Old 11-02-2007, 11:19 PM
Peter Alfke
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Posts: n/a
Default Re: Another way to handle floating inputs.

Kolja, I see it differently:
A weak keeper has two disadvantages:
It is weak, and might be overridden by crosstalk
It consumes constant power when the signal is pulled Low.

The intelligent output driver is stronger in pulling High, thus
offering better protection against crosstalk,
and it consumes no power when it has been pulled Low.
Obviously, any external driver must be strong enough to overcome the
active driver foe a few ns. That's the balancing act.
Peter Alfke

On Nov 2, 11:04 am, "comp.arch.fpga" <[email protected]> wrote:
> Why not use a weak keeper instead?
> Older Xilinx part used that internally on tristate lines. You have a
> weak buffer that drives the line to the voltage seen on the line.
> An undriven line will quickly be driven to either 1 or 0 due to
> initial noise. Another circuit driving the line will need to overcome
> the keeper current (similar to a switching sram cell). The upside is:
> There is no static current (unlike the pullup resistor).
>
> Kolja Sulimma



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  #14 (permalink)  
Old 11-03-2007, 01:19 AM
Jim Granville
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Posts: n/a
Default Re: Another way to handle floating inputs.

Peter Alfke wrote:

> Kolja, I see it differently:
> A weak keeper has two disadvantages:
> It is weak, and might be overridden by crosstalk
> It consumes constant power when the signal is pulled Low.


What you have described is a pullup ?
Keepers, also called Bus-hold, or PinKeepers (depends on which vendor
you are), are snap-action positive feedback 'very light' drivers, and
they draw no power in either state. (typically hundreds of uA)

Of course, a disadvantage of that, is the Pin state is now undefined at
PowerUP, and that may be a bad thing.

The smarter CPLDs allow you to choose Pullup/PinKeep on a per pin basis.

-jg

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  #15 (permalink)  
Old 11-04-2007, 05:22 PM
Peter Alfke
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Posts: n/a
Default Re: Another way to handle floating inputs.

On Nov 2, 4:19 pm, Jim Granville <[email protected]>
wrote:
> Peter Alfke wrote:
> > Kolja, I see it differently:
> > A weak keeper has two disadvantages:
> > It is weak, and might be overridden by crosstalk
> > It consumes constant power when the signal is pulled Low.

>
> What you have described is a pullup ?
> Keepers, also called Bus-hold, or PinKeepers (depends on which vendor
> you are), are snap-action positive feedback 'very light' drivers, and
> they draw no power in either state. (typically hundreds of uA)
>
> Of course, a disadvantage of that, is the Pin state is now undefined at
> PowerUP, and that may be a bad thing.
>
> The smarter CPLDs allow you to choose Pullup/PinKeep on a per pin basis.
>
> -jg


Since Xilinx FPGAs never had weak keepers on the user I/O, I got the
nomenclature confused. Sorry.
You can of course emulate a weak keeper by using the output driver at
its weakest setting, but that may still be too strong in some
applications (but not for switch debouncing).
BTW, I should have mentioned that the switch must be break-before-make
(obviously).
Peter Alfke

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  #16 (permalink)  
Old 11-05-2007, 12:15 PM
RCIngham
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Posts: n/a
Default Re: Another way to handle floating inputs.

>Be specific. What do you mean by "this" ? Your posting is #10 in a
>thread...
>Peter Alfke
>
>On Nov 2, 3:10 am, "RCIngham" <[email protected]> wrote:
>> This looks like "voodoo design" to me.
>> Seehttp://foldoc.org/?voodoo+programmingfor the software equivalent.
>>
>> If you know what the problem really is, design for that. Use series or
>> parallel termination to mitigate ground-bounce, for instance.

>


The originally-posted circuit and the various minor modifications to it t
cover for unknown circumstances...

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  #17 (permalink)  
Old 11-05-2007, 06:49 PM
Peter Alfke
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Posts: n/a
Default Re: Another way to handle floating inputs.

My memory served me poorly, and Ed McGettigan corrected me, thanks:

Virtex outputs have an optional week keeper. as described in the User
guide:

PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF
When using 3-state output (OBUFT) or bidirectional (IOBUF) buffers,
the output can havea weak pull-up resistor, a weak pull-down resistor,
or a weak "keeper" circuit. For input IBUF) buffers, the input can
have either a weak pull-up resistor or a weak pull-down resistor. This
feature can be invoked by adding the following possible constraint
values to the relevant net of the buffers:
PULLUP
PULLDOWN
KEEPER



On Nov 4, 9:22 am, Peter Alfke <[email protected]> wrote:
> On Nov 2, 4:19 pm, Jim Granville <[email protected]>
> wrote:
>
>
>
> > Peter Alfke wrote:
> > > Kolja, I see it differently:
> > > A weak keeper has two disadvantages:
> > > It is weak, and might be overridden by crosstalk
> > > It consumes constant power when the signal is pulled Low.

>
> > What you have described is a pullup ?
> > Keepers, also called Bus-hold, or PinKeepers (depends on which vendor
> > you are), are snap-action positive feedback 'very light' drivers, and
> > they draw no power in either state. (typically hundreds of uA)

>
> > Of course, a disadvantage of that, is the Pin state is now undefined at
> > PowerUP, and that may be a bad thing.

>
> > The smarter CPLDs allow you to choose Pullup/PinKeep on a per pin basis.

>
> > -jg

>
> Since Xilinx FPGAs never had weak keepers on the user I/O, I got the
> nomenclature confused. Sorry.
> You can of course emulate a weak keeper by using the output driver at
> its weakest setting, but that may still be too strong in some
> applications (but not for switch debouncing).
> BTW, I should have mentioned that the switch must be break-before-make
> (obviously).
> Peter Alfke



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