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Old 10-30-2003, 06:22 PM
Dave Vanden Bout
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Default ANNC: WebPACK 6.1 tutorials

We have released two tutorials that show how to create FPGA designs
using Xilinx WebPACK 6.1:

http://www.xess.com/appnotes/webpack-6_1-xsa.pdf
This tutorial shows design examples for a SpartanII FPGA on an XESS
XSA Board.

http://www.xess.com/appnotes/webpack-6_1-xsb.pdf
This tutorial shows design examples for a SpartanIIE FPGA on an XESS
XSB Board.

At the risk of providing too much information, here is a list of topics
covered in these tutorials:


> This tutorial shows the use of the WebPACK tools on two simple design examples:
>
> an LED decoder and
> a counter which displays its current value on a seven-segment LED.
>
> Along the way, you will see:
> How to start an FPGA project.
> How to target a design to a particular type of FPGA.
> How to describe a logic circuit using VHDL and/or schematics.
> How to detect and fix VHDL syntactical errors.
> How to synthesize a netlist from a circuit description.
> How to fit the netlist into an FPGA.
> How to check device utilization and timing for an FPGA.
> How to generate a bitstream for an FPGA.
> How to download a bitstream to program an FPGA.
> How to test the programmed FPGA.
>

--
|| Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
|| [email protected] PO Box 33091 ||
|| http://www.xess.com Raleigh NC 27636 USA FAX919) 367-2946 ||


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  #2 (permalink)  
Old 10-30-2003, 09:10 PM
Glen Herrmannsfeldt
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Default Re: WebPACK 6.1 tutorials


"Dave Vanden Bout" <[email protected]> wrote in message
news:[email protected]
> We have released two tutorials that show how to create FPGA designs
> using Xilinx WebPACK 6.1:


(snip)

> > Along the way, you will see:
> > How to start an FPGA project.
> > How to target a design to a particular type of FPGA.
> > How to describe a logic circuit using VHDL and/or schematics.
> > How to detect and fix VHDL syntactical errors.
> > How to synthesize a netlist from a circuit description.
> > How to fit the netlist into an FPGA.
> > How to check device utilization and timing for an FPGA.
> > How to generate a bitstream for an FPGA.
> > How to download a bitstream to program an FPGA.
> > How to test the programmed FPGA.


I have downloaded it, but not tried it yet. I do wonder if there is any
support for verilog?

-- glen


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  #3 (permalink)  
Old 10-30-2003, 11:22 PM
Dave Vanden Bout
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Default Re: WebPACK 6.1 tutorials

Glen Herrmannsfeldt wrote:

> "Dave Vanden Bout" <[email protected]> wrote in message
> news:[email protected]
> > We have released two tutorials that show how to create FPGA designs
> > using Xilinx WebPACK 6.1:

>
> (snip)
>
> > > Along the way, you will see:
> > > How to start an FPGA project.
> > > How to target a design to a particular type of FPGA.
> > > How to describe a logic circuit using VHDL and/or schematics.
> > > How to detect and fix VHDL syntactical errors.
> > > How to synthesize a netlist from a circuit description.
> > > How to fit the netlist into an FPGA.
> > > How to check device utilization and timing for an FPGA.
> > > How to generate a bitstream for an FPGA.
> > > How to download a bitstream to program an FPGA.
> > > How to test the programmed FPGA.

>
> I have downloaded it, but not tried it yet. I do wonder if there is any
> support for verilog?
>
> -- glen


WebPACK supports Verilog. You will go through the same operations, dialogs,
windows, etc whether you use Verilog or VHDL so the tutorial should still be
applicable. The only added effort is to develop your own Verilog code to
replace the VHDL already given for the LED decoder and the counter.


--
|| Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
|| [email protected] PO Box 33091 ||
|| http://www.xess.com Raleigh NC 27636 USA FAX919) 367-2946 ||


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  #4 (permalink)  
Old 10-31-2003, 06:10 AM
Glen Herrmannsfeldt
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Posts: n/a
Default Re: WebPACK 6.1 tutorials


"Dave Vanden Bout" <[email protected]> wrote in message
news:[email protected]

> WebPACK supports Verilog. You will go through the same operations,

dialogs,
> windows, etc whether you use Verilog or VHDL so the tutorial should still

be
> applicable. The only added effort is to develop your own Verilog code to
> replace the VHDL already given for the LED decoder and the counter.


Thanks. There was once a discussion that seemed to say that verilog is used
for ASICs and VHDL for FPGA's. I wanted to be sure.

-- glen


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