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Old 02-04-2005, 05:52 PM
Nicolas Matringe
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Default Altera, QuartusII and internal tristates

Hello
For some reasons I have an IP with bidirectionnal IOs that is
instantiated inside a higher level wrapper and that I can't modify. The
proble is that the wrapper inserts some logic between an IO bus of the
IP and the actual chip IOs.
It seems that QuartusII (4.2) produces garbage from my VHDL. How can I do?

The problem is that int_bus is x"FF" when en = '1', instead of int_bus_in.

Sample code :

entity wrapper is
port (
io_bus_1 : inout std_logic_vector(31 downto 0);
io_bus_2 : inout std_logic_vector(31 downto 0);
.... );
end entity wrapper;

architecture str of wrapper is
signal en : std_logic;
signal int_bus_in : std_logic_vector(7 downto 0);
signal int_bus_out : std_logic_vector(7 downto 0);
signal int_bus : std_logic_vector(7 downto 0);

component ip is
port(
io_bus_1 : inout std_logic_vector(7 downto 0);
io_bus_2 : inout std_logic_vector(7 downto 0);
ctrl : out std_logic;
.... );
end component ip;

begin

ip_inst : ip
port map (
io_bus_1 => int_bus,
io_bus_2 => io_bus_2(7 downto 0),
ctrl => en,
... );

int_bus_out <= int_bus;
int_bus <= int_bus_in when en = '1' else (others => 'Z');


end str;
--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
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  #2 (permalink)  
Old 02-05-2005, 04:45 AM
Subroto Datta
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Posts: n/a
Default Re: Altera, QuartusII and internal tristates

Hi Nicolas,

If the wrapper is really inserting logic between a bidirectional IO bus of
the IP and the user pins then the IO bus will be converted to multiplexer
logic (as we can't implement tristate buses internally on the chip). It is
not clear that this is happening, because the 'en' signal in the design is
driven from the lower-level component.

If you send me a qar (Project->Archive) of your design, it will be easy for
us to tell you what is happening. Please email the qar file to the email
address for this post.

Subroto Datta,
Altera Corp.

"Nicolas Matringe" <[email protected]> wrote in message
news:[email protected]
> Hello
> For some reasons I have an IP with bidirectionnal IOs that is instantiated
> inside a higher level wrapper and that I can't modify. The proble is that
> the wrapper inserts some logic between an IO bus of the IP and the actual
> chip IOs.
> It seems that QuartusII (4.2) produces garbage from my VHDL. How can I do?
>
> The problem is that int_bus is x"FF" when en = '1', instead of int_bus_in.
>
> Sample code :
>
> entity wrapper is
> port (
> io_bus_1 : inout std_logic_vector(31 downto 0);
> io_bus_2 : inout std_logic_vector(31 downto 0);
> ... );
> end entity wrapper;
>
> architecture str of wrapper is
> signal en : std_logic;
> signal int_bus_in : std_logic_vector(7 downto 0);
> signal int_bus_out : std_logic_vector(7 downto 0);
> signal int_bus : std_logic_vector(7 downto 0);
>
> component ip is
> port(
> io_bus_1 : inout std_logic_vector(7 downto 0);
> io_bus_2 : inout std_logic_vector(7 downto 0);
> ctrl : out std_logic;
> ... );
> end component ip;
>
> begin
>
> ip_inst : ip
> port map (
> io_bus_1 => int_bus,
> io_bus_2 => io_bus_2(7 downto 0),
> ctrl => en,
> ... );
>
> int_bus_out <= int_bus;
> int_bus <= int_bus_in when en = '1' else (others => 'Z');
>
>
> end str;
> --
> ____ _ __ ___
> | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
> | | | | | (_| |_| | Invalid return address: remove the -
> |_| |_|_|\__|\___/



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