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Old 03-03-2005, 04:22 PM
Manfred Balik
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Default Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem

I'm using an Altera APEX20KE with 200k gates on a bought FPGA board.
The Clocks 1 and 2 of the FPGA are used by the board, the Clocks 3 and 4 are
free.
I testet the i2c-core from opencores.org working with the onboard clock on
Clock-Pin 2 and it works fine.
If I connect (just connect not use in the FPGA, I'm still using the onboard
clock from Clock-Pin 2) an own clock to the two free Clock-Pins, the
i2c-core doesn't work anymore !!! :-(
If I use my own clock on Clock-Pin 3 or 4 as clock-input for the i2c-core,
it doesn't work too.
I can't understand this behaviour !?!?!?

If I put in the Altera Megafunction altclklock at the input of Clock2 and
Clock4 Quartus II 4.2 SP1 can't fit. The Error Messages of the Fitter are:
Error: Project requires too many 2 ClockLock PLLs, but the selected
device can contain only 0 ClockLock PLLs
Error: Project requires 2 signals of type clock output, but the target
device can contain only 1 signals
Error: Can't fit design in device
Error: Quartus II Fitter was unsuccessful. 3 errors, 0 warnings
but the APEX20KE: EP20K200EFC672-3 has 2 PLLs according to the data
sheet!!!!
Is this an Error in Quartus or mine???

Please Help

Manfred Balik



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Old 03-03-2005, 05:49 PM
Peter Sommerfeld
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Default Re: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem

Hi Manfred, I'm not familiar with Apex too much but I know on Stratix
certain PLL can ONLY be instatiated with certain dedicated clock pins,
ie. the PLL # has to match the clock pin, otherwise a no-fit occurs. I
suspect this is your problem. Check the Apex docs, or swap the clock
pins that feed your PLLs.

HTH, Pete

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Old 03-03-2005, 06:10 PM
Ben Twijnstra
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Default Re: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem

Hi Manfred,

> but the APEX20KE: EP20K200EFC672-3 has 2 PLLs according to the data
> sheet!!!!
> Is this an Error in Quartus or mine???


The EP20K200Exxx-1X and -2X have proper PLLs, the others don't. All the
bigger 20KEs have PLLs, but in the non-X version these haven't been tested
and might therefore be defective.

If this is a recently-produced device and doesn't push the edge of
performance of the -3, you might want to classify it as a -2X and see how
well you fare in practice, but don't try this if you're going to actually
produce something with a -3 posing as a -2X.

Best regards,


Ben

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  #4 (permalink)  
Old 03-04-2005, 08:04 AM
Manfred Balik
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Default Re: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem

I'm using the right clock pins (if I understand the data sheet correct)!
.... and this is the behaviour I don't understand :-(
Manfred

"Peter Sommerfeld" <[email protected]> schrieb im Newsbeitrag
news:[email protected] oups.com...
> Hi Manfred, I'm not familiar with Apex too much but I know on Stratix
> certain PLL can ONLY be instatiated with certain dedicated clock pins,
> ie. the PLL # has to match the clock pin, otherwise a no-fit occurs. I
> suspect this is your problem. Check the Apex docs, or swap the clock
> pins that feed your PLLs.
>
> HTH, Pete
>



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