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  #1 (permalink)  
Old 10-06-2005, 12:56 PM
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Default Altera Gate Delay Simulation

I am doing some work targeted to StratixGX family for me RTL or gate
delay simulation is a must.

Can i do a post synthesis simulation in Modelsim for stratix GX Family
using the synthesis output design.vho file from QuartusII.
But this simulation should include gate delays specifically.

as like in Xilinx I can do a pre Map simulation which gives gate
delays.

Please mail me on [email protected]

Regards
Kedar

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  #2 (permalink)  
Old 10-06-2005, 09:35 PM
Ben Twijnstra
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Default Re: Altera Gate Delay Simulation

Hi kedar,

> I am doing some work targeted to StratixGX family for me RTL or gate
> delay simulation is a must.
>
> Can i do a post synthesis simulation in Modelsim for stratix GX Family
> using the synthesis output design.vho file from QuartusII.
> But this simulation should include gate delays specifically.
>
> as like in Xilinx I can do a pre Map simulation which gives gate
> delays.


Modelsim has the option to use a so-called SDF backannotation file to use
the gate (and wire) delays. Quartus generates the delay backannotation file
as <yourdesign>.sdo. For more info, look up SDF in the Modelsim manual.

Best regards,


Ben

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  #3 (permalink)  
Old 10-07-2005, 04:24 AM
morpheus
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Default Re: Altera Gate Delay Simulation

Hey,
I have been dealing with this situation as well. When you compile the
design, look in the project folder under modelsim sub folder, you
should be able to find a .vo or .vho file depending upon your settings
for verilog or vhdl in quartus II.
Create a project in Modelsim and add the .vo or .vho file along with
the stratix GX atoms file, u should be able to get it from altera
website.
For gate delay simulation, get the .sdo file from the design's project
folder. When simulating in Modelsim, choose the SDO tab and add this
..sdo file there and then simulate...its MAGIC!!!
later
MORPHEUS

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  #4 (permalink)  
Old 10-10-2005, 08:36 AM
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Default Re: Altera Gate Delay Simulation

Hi Morpheus And Ben

Thanks for your reply but my confusion is
1. In Quartus tool Full Compilation means complete implementation and
that generates both .vho and .sdo file for me after fitting and place
route.

2. But is there any option to generate a back anotated post synthesis
..vhd file or .vho file with a .sdo file after gate level synthesis

so after simulating the post synthesis .sdo file can we get only gate
delays in simulation and not the net or routing delays

thanks
regards

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  #5 (permalink)  
Old 10-10-2005, 08:37 AM
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Default Re: Altera Gate Delay Simulation

Hi Morpheus And Ben

Thanks for your reply but my confusion is
1. In Quartus tool Full Compilation means complete implementation and
that generates both .vho and .sdo file for me after fitting and place
route.

2. But is there any option to generate a back anotated post synthesis
..vhd file or .vho file with a .sdo file after gate level synthesis

so after simulating the post synthesis .sdo file can we get only gate
delays in simulation and not the net or routing(wire) delays

thanks
regards
Kedar

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  #6 (permalink)  
Old 10-21-2005, 11:43 PM
Albert Chang
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Default Re: Altera Gate Delay Simulation

Hi Kedar,

To generate a post-synthesis netlist along with an SDO timing file, use
the following commands:

quartus_map <project name> -c <revision>
quartus_tan <project name> -c <revision> --post_map --zero_ic_delays
quartus_eda <project name> -c <revision> --simulation --tool=<toolname>
--format=verilog

When you generate the VO/VHO and SDO file using the quartus_eda
executable, you will receive the following warning message:

Warning: Standard Delay Output File (.sdo) contains estimated delays --
run Fitter first to annotate SDF Output File with exact delays

After you perform your post-synthesis simulations, Altera recommends
that you complete a full compilation and regenerate the VO/VHO and SDO
files to include exact delays of your design for gate-level timing
simulations. A full compilation in the Quartus II software includes
synthesis, placement and route.

For more information, please refer to the following solution
http://www.altera.com/support/kdb/20...92005_405.html

If you do not want to wait for a full place-and-route, you can use the
Early Timing Estimator, in the Quartus II software, to perform a
preliminary place-and-route in a fraction of the time of a full
place-and-route. After the Early Timing Estimator, you can generate a
simulation netlist with the early timing estimates.

Albert Chang
Senior Applications Engineer
Altera Corporation

[email protected] wrote:
> Hi Morpheus And Ben
>
> Thanks for your reply but my confusion is
> 1. In Quartus tool Full Compilation means complete implementation and
> that generates both .vho and .sdo file for me after fitting and place
> route.
>
> 2. But is there any option to generate a back anotated post synthesis
> .vhd file or .vho file with a .sdo file after gate level synthesis
>
> so after simulating the post synthesis .sdo file can we get only gate
> delays in simulation and not the net or routing(wire) delays
>
> thanks
> regards
> Kedar


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