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-   -   altera async fifo with different read/write port widths? (http://www.fpgacentral.com/group/showthread.php?t=58415)

fpgabuilder 04-22-2006 01:32 AM

altera async fifo with different read/write port widths?
 
Does anyone know if Altera has any prebuilt async fifo with different
read/write ports? I am trying to target Cyclone device. The M4K
blocks do allow variable width read/write ports but I cannot see any
fifos made using those.

TIA


Rob 04-22-2006 03:27 AM

Re: altera async fifo with different read/write port widths?
 
Try the lpm_fifo MegaWizard function. You can use separate read and write
ports that are driven from two different unsynchronized clocks.

"fpgabuilder" <[email protected]> wrote in message
news:[email protected] ups.com...
> Does anyone know if Altera has any prebuilt async fifo with different
> read/write ports? I am trying to target Cyclone device. The M4K
> blocks do allow variable width read/write ports but I cannot see any
> fifos made using those.
>
> TIA
>





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