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  #1 (permalink)  
Old 05-16-2005, 01:54 PM
Nicolas Matringe
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Default Altera Apex20KE PLL output jitter problem

Hello
I have a design based on an Apex20K400E which uses the AltClockBoost to
generate a 48MHz output clock from a 60MHz source.
My problem is that I need a very low jitter and the best I can achieve
is around +/-400ps.
The datasheet gives two numbers for the generated clock jitter:
either 200ps, or 0.35% of the generated period (that would be 73ps).
How can I obtain such results?

Nicolas

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  #2 (permalink)  
Old 05-24-2005, 06:47 PM
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Default Re: Altera Apex20KE PLL output jitter problem

Nicolas,
The output jitter spec on APEX 20KE devices is .35% of output period,
but it is RMS, not peak-to-peak. The conversion from RMS to
peak-to-peak depends on the desired bit error rate and the observation
period. But if you are getting 800 ps total jitter, that is reasonable
for a 73 ps RMS jitter.

So the next question on your mind will be "How to reduce output
jitter?"

First off, examine your input jitter. The device spec is 2% of the
input period peak-to-peak, so 333 ps peak-to-peak jitter is acceptable.
However, reducing the input jitter can reduce your output jitter in
some circumstances. The key factor is the frequency of periodic jitter
components. The bandwidth of the APEX 20KE PLL is around 5 MHz, so
jitter below that frequency will pass but jitter above that frequency
will be attenuated. For example, if the 60 MHz input signal is
modulated by a nearby 1 MHz signal, then that 1 MHz jitter will pass
through the PLL. On the other hand if it the jitter is random jitter,
or higher-frequency jitter, then the PLL will attenuate this jitter.

To break this down to practical advice, take a look at the jitter of
your clock source with a tool like an Agilent DCAJ, LeCroy SDA6000A, or
Wavecrest. These can break down the jitter into deterministic and
random components, and also can show you information about the
frequency components of the jitter. For example if the clock is coming
from an oscillator that is routed through another device like a CPLD
you may be picking up some jitter there.

The second thing to look at on the system is the board layout of the
APEX device. The APEX devices have separate VCC and GND pins for each
PLL, and these should be isolated from the VCC and GND used by the
logic or IOs of the device. There's also a separate VCC and GND pin for
the clock output, and again you may want to isolate these VCC and GND
pins from other ones, otherwise noise on VCCIO will show up as jitter
on the clock output. You can determine if these are the problem by
looking at jitter with and without the logic and IOs toggling - if the
jitter is worse with toggling then this would be a good place to look.
App Note 115 on the Altera web site has some more details.
http://www.altera.com/literature/an/an115.pdf

Sincerely,
Greg Steinke
Altera Corporation
[email protected]

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  #3 (permalink)  
Old 05-24-2005, 07:17 PM
austin
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Default Re: Altera Apex20KE PLL output jitter problem

Also note that jitter is transferred from the core, power, and IOs to
the PLL.

See out technical note:

http://www.xilinx.com/products/virte...pic/vtt013.pdf

Austin


[email protected] wrote:

> Nicolas,
> The output jitter spec on APEX 20KE devices is .35% of output period,
> but it is RMS, not peak-to-peak. The conversion from RMS to
> peak-to-peak depends on the desired bit error rate and the observation
> period. But if you are getting 800 ps total jitter, that is reasonable
> for a 73 ps RMS jitter.
>
> So the next question on your mind will be "How to reduce output
> jitter?"
>
> First off, examine your input jitter. The device spec is 2% of the
> input period peak-to-peak, so 333 ps peak-to-peak jitter is acceptable.
> However, reducing the input jitter can reduce your output jitter in
> some circumstances. The key factor is the frequency of periodic jitter
> components. The bandwidth of the APEX 20KE PLL is around 5 MHz, so
> jitter below that frequency will pass but jitter above that frequency
> will be attenuated. For example, if the 60 MHz input signal is
> modulated by a nearby 1 MHz signal, then that 1 MHz jitter will pass
> through the PLL. On the other hand if it the jitter is random jitter,
> or higher-frequency jitter, then the PLL will attenuate this jitter.
>
> To break this down to practical advice, take a look at the jitter of
> your clock source with a tool like an Agilent DCAJ, LeCroy SDA6000A, or
> Wavecrest. These can break down the jitter into deterministic and
> random components, and also can show you information about the
> frequency components of the jitter. For example if the clock is coming
> from an oscillator that is routed through another device like a CPLD
> you may be picking up some jitter there.
>
> The second thing to look at on the system is the board layout of the
> APEX device. The APEX devices have separate VCC and GND pins for each
> PLL, and these should be isolated from the VCC and GND used by the
> logic or IOs of the device. There's also a separate VCC and GND pin for
> the clock output, and again you may want to isolate these VCC and GND
> pins from other ones, otherwise noise on VCCIO will show up as jitter
> on the clock output. You can determine if these are the problem by
> looking at jitter with and without the logic and IOs toggling - if the
> jitter is worse with toggling then this would be a good place to look.
> App Note 115 on the Altera web site has some more details.
> http://www.altera.com/literature/an/an115.pdf
>
> Sincerely,
> Greg Steinke
> Altera Corporation
> [email protected]
>

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  #4 (permalink)  
Old 05-24-2005, 09:56 PM
John_H
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Posts: n/a
Default Re: Altera Apex20KE PLL output jitter problem

Thanks for the info, Austin (and Greg).

So the question goes back to Altera:
Was the "NIOS Development Board from Altera" which "features a PLL-capable
APEX EP20K200E-2X" laid out with good, low-noise design rules for planes for
the VCC_CKOUT2 and GND_CKOUT2?

I've never considered any FPGA or CPLD to be capable of producing very low
jitter outputs because of all the digital activity going. The Xilinx noise
seminar suggested (my impression) that only signals within an I/O bank
*significantly* change the noise characteristics of an I/O on that bank; the
effect from signals in other banks is negligible. If a clock output was the
only output on a bank (the CKOUT2 realm perhaps?) perhaps noise could me
mitigated.

While the Xilinx "Tech Topic" results are from a competitor, the equipment
and setups should be solid. So, did Altera do their job right with the
board? Or are there other Altera documents to support the use of a digital
circuit in a precision analog system?


"austin" <[email protected]> wrote in message
news:[email protected]
> Also note that jitter is transferred from the core, power, and IOs to
> the PLL.
>
> See out technical note:
>
> http://www.xilinx.com/products/virte...pic/vtt013.pdf
>
> Austin
>
>
> [email protected] wrote:
>
> > Nicolas,
> > The output jitter spec on APEX 20KE devices is .35% of output period,
> > but it is RMS, not peak-to-peak. The conversion from RMS to
> > peak-to-peak depends on the desired bit error rate and the observation
> > period. But if you are getting 800 ps total jitter, that is reasonable
> > for a 73 ps RMS jitter.
> >
> > So the next question on your mind will be "How to reduce output
> > jitter?"
> >
> > First off, examine your input jitter. The device spec is 2% of the
> > input period peak-to-peak, so 333 ps peak-to-peak jitter is acceptable.
> > However, reducing the input jitter can reduce your output jitter in
> > some circumstances. The key factor is the frequency of periodic jitter
> > components. The bandwidth of the APEX 20KE PLL is around 5 MHz, so
> > jitter below that frequency will pass but jitter above that frequency
> > will be attenuated. For example, if the 60 MHz input signal is
> > modulated by a nearby 1 MHz signal, then that 1 MHz jitter will pass
> > through the PLL. On the other hand if it the jitter is random jitter,
> > or higher-frequency jitter, then the PLL will attenuate this jitter.
> >
> > To break this down to practical advice, take a look at the jitter of
> > your clock source with a tool like an Agilent DCAJ, LeCroy SDA6000A, or
> > Wavecrest. These can break down the jitter into deterministic and
> > random components, and also can show you information about the
> > frequency components of the jitter. For example if the clock is coming
> > from an oscillator that is routed through another device like a CPLD
> > you may be picking up some jitter there.
> >
> > The second thing to look at on the system is the board layout of the
> > APEX device. The APEX devices have separate VCC and GND pins for each
> > PLL, and these should be isolated from the VCC and GND used by the
> > logic or IOs of the device. There's also a separate VCC and GND pin for
> > the clock output, and again you may want to isolate these VCC and GND
> > pins from other ones, otherwise noise on VCCIO will show up as jitter
> > on the clock output. You can determine if these are the problem by
> > looking at jitter with and without the logic and IOs toggling - if the
> > jitter is worse with toggling then this would be a good place to look.
> > App Note 115 on the Altera web site has some more details.
> > http://www.altera.com/literature/an/an115.pdf
> >
> > Sincerely,
> > Greg Steinke
> > Altera Corporation
> > [email protected]
> >



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  #5 (permalink)  
Old 05-27-2005, 09:27 AM
Nicolas Matringe
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Default Re: Altera Apex20KE PLL output jitter problem

Thanks a lot Greg, though your answer comes a bit late since my client
has already accepted the product and decided to use an external PLL for
his application.

I am not a jitter specialist and I don't know exactly what peak-to-peak
and RMS jitter are.
Let's try to clarify a bit:
- RMS jitter is a mean value (probably something like the square root
of the sum of the squares of the differences between tehoretical period
and actual period)
- p2p jitter is the maximum difference between theoretical period and
actual period.
Am i right?

What we did is compare the 60MHz input with the 48MHz output (sync'ing
the scope was a bit of a nightmare but that's another matter ) and we
saw looked a bit like that:
(look with a fixed-size font)
_______ _______
60MHz ___/ \_______/ \
_________ ____
48MHz __/ \\________//

Nicolas

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  #6 (permalink)  
Old 05-27-2005, 03:48 PM
Austin Lesea
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Default Re: Altera Apex20KE PLL output jitter problem

Nicolas,

http://tinyurl.com/4mvcw

Details the definitions of jitter, and some common causes, and
measurement issues.

Austin

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