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Old 01-07-2004, 03:19 AM
Bhadri
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Default AFX BG560 board

Hello
I am trying to use AFX BG560-100 board from
xilinx.(http://www.xilinx.com/xlnx/xebiz/boa...-100&category=)
I have XCV 1000 fgpa chips to use with the board.
I have never used this board before.I was using Dililentinc board till
this.
1.Can anyone tell me how to start using this board for simple
applications.
2.How to use the prototype area in the board.
3.can i use the same ISE webpack software 5.1i to program this chips
with the board or is there any other software.

Thanks in advance.It would be of great help.
bhadri.
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  #2 (permalink)  
Old 01-07-2004, 06:04 AM
Adam
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Default Re: AFX BG560 board

I just used this board for my project a few weeks ago but this is off the
top of my head so some things may be wrong. My goal was only a 30-40 cycle
test at 15MHz. You should have the protoboard datasheet and the XCV1000
datasheet handy as you will reference them a lot when you constrain your
I/O. You will also need a 3.3v and 2.5v power supply in addition to a
download cable. I used a MultiLinx in slave-serial mode. There are jumpers
on the board to specify which download mode you are using.
The Virtex has 'banks' of I/O that can each run on its own supply voltage.
This is set by a row of jumpers on the left side of the AFX board. The
board I used already had all I/O banks jumpered to the 3.3 supply. The
VccINT post powers the chip core. For an XCV1000 this is 2.5v(****check the
datasheet to be sure****). You should be aware that your design must
specify the I/O type to use(LVTTL, LVDS, etc)
In the Virtex datasheet you will find the pinouts for the 560BGA package
labeled with two alphanumeric characters(such as AR or B4). These
correspond to the prototype area holes around the chip on the AFX board.
*Note* that some rows and columns are entirely ground. Since my I/O usage
was small(16-20 pins), I simply inserted the headers that come with the
board into a row that had a lot of consecutive general I/O pins. I then just
attached my logic analyzer cable to these headers. I discovered that they
don't make good contact unless slightly pressed against but other than that
worked fine.
There may or may nor be a clock chip already on your board. The four
sockets at each corner of the chip holder are for clock chips. If one is
populated make sure you don't attempt to use another external clock on the
same pin. Pin AL or AK I think is the lower left clock chip.
You won't be able to use Webpack because the XCV1000 is larger than the
V300E device, the largest Webpack supports. You will need the real ISE to
program.

Adam

"Bhadri" <[email protected]> wrote in message
news:[email protected] om...
> Hello
> I am trying to use AFX BG560-100 board from
>

xilinx.(http://www.xilinx.com/xlnx/xebiz/boa...HW-AFX-BG560-1
00&category=)
> I have XCV 1000 fgpa chips to use with the board.
> I have never used this board before.I was using Dililentinc board till
> this.
> 1.Can anyone tell me how to start using this board for simple
> applications.
> 2.How to use the prototype area in the board.
> 3.can i use the same ISE webpack software 5.1i to program this chips
> with the board or is there any other software.
>
> Thanks in advance.It would be of great help.
> bhadri.



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  #3 (permalink)  
Old 01-16-2004, 08:35 PM
Bhadri
Guest
 
Posts: n/a
Default Re: AFX BG560 board

Hello Adam

Thanks for ur reply in Google.com for my question about AFX Board.I
have few more Doubts and it would be great if u would help me with
that.Sorry more bothering you.

1.Now Once i download the configuration file to the fpga then i can use
the area surrounding the Chip for reading out values in each pin
through those area with logical analyzer.But why do we need the prototype
area in the board on the left side.How can i use that.
2. Then to specify the I/O type.What is that.I am not clear.(your
design must
specify the I/O type to use(LVTTL, LVDS, etc)).If possible can u send
me an simple code like showing this.

Thanks
Regards
Bhadri
"Adam" <[email protected]> wrote in message news:<[email protected]>. ..
> I just used this board for my project a few weeks ago but this is off the
> top of my head so some things may be wrong. My goal was only a 30-40 cycle
> test at 15MHz. You should have the protoboard datasheet and the XCV1000
> datasheet handy as you will reference them a lot when you constrain your
> I/O. You will also need a 3.3v and 2.5v power supply in addition to a
> download cable. I used a MultiLinx in slave-serial mode. There are jumpers
> on the board to specify which download mode you are using.
> The Virtex has 'banks' of I/O that can each run on its own supply voltage.
> This is set by a row of jumpers on the left side of the AFX board. The
> board I used already had all I/O banks jumpered to the 3.3 supply. The
> VccINT post powers the chip core. For an XCV1000 this is 2.5v(****check the
> datasheet to be sure****). You should be aware that your design must
> specify the I/O type to use(LVTTL, LVDS, etc)
> In the Virtex datasheet you will find the pinouts for the 560BGA package
> labeled with two alphanumeric characters(such as AR or B4). These
> correspond to the prototype area holes around the chip on the AFX board.
> *Note* that some rows and columns are entirely ground. Since my I/O usage
> was small(16-20 pins), I simply inserted the headers that come with the
> board into a row that had a lot of consecutive general I/O pins. I then just
> attached my logic analyzer cable to these headers. I discovered that they
> don't make good contact unless slightly pressed against but other than that
> worked fine.
> There may or may nor be a clock chip already on your board. The four
> sockets at each corner of the chip holder are for clock chips. If one is
> populated make sure you don't attempt to use another external clock on the
> same pin. Pin AL or AK I think is the lower left clock chip.
> You won't be able to use Webpack because the XCV1000 is larger than the
> V300E device, the largest Webpack supports. You will need the real ISE to
> program.
>
> Adam
>
> "Bhadri" <[email protected]> wrote in message
> news:[email protected] om...
> > Hello
> > I am trying to use AFX BG560-100 board from
> >

> xilinx.(http://www.xilinx.com/xlnx/xebiz/boa...HW-AFX-BG560-1
> 00&category=)
> > I have XCV 1000 fgpa chips to use with the board.
> > I have never used this board before.I was using Dililentinc board till
> > this.
> > 1.Can anyone tell me how to start using this board for simple
> > applications.
> > 2.How to use the prototype area in the board.
> > 3.can i use the same ISE webpack software 5.1i to program this chips
> > with the board or is there any other software.
> >
> > Thanks in advance.It would be of great help.
> > bhadri.

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  #4 (permalink)  
Old 01-20-2004, 05:56 AM
Adam
Guest
 
Posts: n/a
Default Re: AFX BG560 board

> Thanks for ur reply in Google.com for my question about AFX Board.I
> have few more Doubts and it would be great if u would help me with
> that.Sorry more bothering you.
>
> 1.Now Once i download the configuration file to the fpga then i can use
> the area surrounding the Chip for reading out values in each pin
> through those area with logical analyzer.But why do we need the prototype
> area in the board on the left side.How can i use that.


You use the prototype area for any other circuitry you may want to interface
to the FPGA. My design had no other circuits so this area was unused. Plus
returning the board back to its original condition after solding to it isn't
easy.

> 2. Then to specify the I/O type.What is that.I am not clear.(your
> design must
> specify the I/O type to use(LVTTL, LVDS, etc)).If possible can u send
> me an simple code like showing this.


Many modern FPGAs support multiple I/O standards. For instance, LVTTL uses
one 3.3 volt signaling line while LVDS uses the voltage difference between
two lines to carry one signal. Here is an app note that describes what each
I/O standard uses: http://www.xilinx.com/bvdocs/appnotes/xapp133.pdf.
So far in my designs with HDLs I use the vendor's schematic entry to do the
top level design. So in my case I created a schematic symbol from my VHDL
design and then placed the symbol along with the I/Os in a schematic. In
the ECS you should see the I/O category and then the various I/O buffers.
In an HDL I believe you have to instantiate the specific primitive available
in the FPGA and then set the attributes. I'm in the process of learning
this way myself.


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