FPGA Central

Dear Sir or Madam,

I have a question concerning Modelsim:

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

Thank you for your help.

Best regards
Andrés Vázquez
G&D

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????

Some additional question:
Is the shown macro for functinal or for timing simulation ?
The background of this question: When I run the simulation and
open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN
I can find the original names of the primary inputs and outputs
but I can NOT find the original internal names, these seem to be
renamed by the compiler.
If I want to analyse a state machine it is impossible without
the original names.

So my question: How can I simulate (functional) without losing
the original names ?

>
> MACRO:
> cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
> vlib modelsim_work
> vmap work modelsim_work
> vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
> vcom -93 -reportprogress 300 -work work
> {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
> vcom -93 -reportprogress 300 -work work
> {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
> view signals
> view wave
> vsim work.TB_PACKETFILE_CTRL
> add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
> add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
> add wave sim:/tb_packetfile_ctrl/u1/Reset
> add wave sim:/tb_packetfile_ctrl/u1/Write
> add wave sim:/tb_packetfile_ctrl/u1/Read
> add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????

ALuPin <[email protected]> wrote in message
news:[email protected] om...
> Some additional question:
> Is the shown macro for functinal or for timing simulation ?
> The background of this question: When I run the simulation and
> open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN
> I can find the original names of the primary inputs and outputs
> but I can NOT find the original internal names, these seem to be
> renamed by the compiler.
> If I want to analyse a state machine it is impossible without
> the original names.
>
> So my question: How can I simulate (functional) without losing
> the original names ?


Off the top of my head, open the Structure window (View->Structure)
and navigate down through your design hierarchy to find the
instantiated component you want. All signal names/state machine
states should be available here. When a signal's selected select
View->Wave->Selected Signals, it's added to the Waveform
window and the command to show it in the waveform window is
displayed at the command prompt in the Main window.

Signals can also be dragged and dropped into the Waveform
window but you don't get the command in the main window.

Hope this helps,

Nial Stewart
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

[email protected] (ALuPin) wrote in message news:<b8a9[email protected] com>...
> Some additional question:
> Is the shown macro for functinal or for timing simulation ?
> The background of this question: When I run the simulation and
> open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN
> I can find the original names of the primary inputs and outputs
> but I can NOT find the original internal names, these seem to be
> renamed by the compiler.
> If I want to analyse a state machine it is impossible without
> the original names.
>
> So my question: How can I simulate (functional) without losing
> the original names ?

You do the functional simulation BEFORE you synthesize and place and
route. Did you do that?

After place-and-route, did the static timing analyzer tell you that
you win?

--a

Hi,

that is the question !
In Altera QuartusII software there is
--> Processing ----> Start Compilation and Simulation

But when starting Modelsim the internal names (I gave the different
signals) are not used anymore with the exception of the inputs
and outputs.
Maybe I should mention that I used megafunctions (RAM structures ... that
I instantiated). But nevertheless the inputs of these megafunctions
should be shown, but they are not!

Andrés

>
> You do the functional simulation BEFORE you synthesize and place and
> route. Did you do that?
>
> After place-and-route, did the static timing analyzer tell you that
> you win?
>
> --a

ALuPin wrote:

> Maybe I should mention that I used megafunctions (RAM structures ... that
> I instantiated).

Consider coding the RAM yourself
using the standard template.
This will allow you to sim your
code instead of a netlist.

-- Mike Treseler