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Old 03-24-2006, 06:59 AM
Nju Njoroge
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Default Accessing ModelSim Environment variables in Verilog code

Hello,

I would like to access environment variables defined in ModelSim (6.0d)
in my Verilog code so that I can use them with the `ifdef construct.
For instance, ModelSim allows you to access the "MODEL_TECH"
environment variable, which is useful for employing `ifdef's on code
you want that you want to be compiled for simulation, but ignored for
hardware synthesis.

In a similar vein, I tried creating and setting my own environment
variable using "setenv MY_VARIABLE 1" in my .do compile tcl script
right before the script compiles my modules. Unfortunately, the Verilog
code is not able to access this env variable. I'm avoiding using an
include file, but if there is not way around this, then that's what
I'll have to do.

Thanks,

NN

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Old 03-24-2006, 06:21 PM
Mike Treseler
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Default Re: Accessing ModelSim Environment variables in Verilog code

Nju Njoroge wrote:

> I would like to access environment variables defined in ModelSim (6.0d)
> in my Verilog code so that I can use them with the `ifdef construct.
> For instance, ModelSim allows you to access the "MODEL_TECH"
> environment variable, which is useful for employing `ifdef's on code
> you want that you want to be compiled for simulation, but ignored for
> hardware synthesis.


From the modelsim TCL prompt you can
get at underlying OS commands using the
tcl _exec_ command. For example, if I
have env and grep on my machine, I can do
things like:

VSIM 17> exec env | grep RSH
# CVS_RSH=ssh

VSIM 18> exec env | grep MODEL
# MODELSIM_TCL=/evtfs/home/tres/tcl/modelsim.tcl
# MODELTECH=/flip/usr1/modeltech
# MODEL_TECH=/flip/usr1/modeltech/linux
# MODEL_TECH_TCL=/flip/usr1/modeltech/linux/../tcl
# MODELSIM=modelsim.ini

But the only interface common to HDL and TCL is a file.

-- Mike Treseler
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Old 03-24-2006, 07:01 PM
Chris Briggs
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Default Re: Accessing ModelSim Environment variables in Verilog code

The thing is that MODEL_TECH isn't an environment variable, it's a
Verilog macro that Modelsim automatically defines for you. It's the
same as if you did `define FOO in your code or +define+FOO on the vlog
command line.

Your choices are to pass your settings on the vlog command line
(+define+MY_VARIABLE=1) or write them to a file (`define MY_VARIABLE 1)
that gets compiled in with your testbench.

-cb

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Old 03-25-2006, 03:26 AM
Nju Njoroge
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Default Re: Accessing ModelSim Environment variables in Verilog code

Chris Briggs wrote:
> The thing is that MODEL_TECH isn't an environment variable, it's a
> Verilog macro that Modelsim automatically defines for you. It's the
> same as if you did `define FOO in your code or +define+FOO on the vlog
> command line.
>
> Your choices are to pass your settings on the vlog command line
> (+define+MY_VARIABLE=1) or write them to a file (`define MY_VARIABLE 1)
> that gets compiled in with your testbench.
>
> -cb

The vlog option is exactly what I was looking for. My Verilog code is
shared with other EDK projects (as part of an EDK pcore), but the do
script that I use is specific to each EDK project.

I just tried your suggestion and it works. This is what I had to add in
my .do script (for those who interesting in getting the syntax right):

# Snippet of my do script
do system.do # Invoke EDK generated do script first
vlog -incr -work my_pcore path_to_verilog_file +define+MY_VARIABLE=1
..
..
..

Now, I can de-couple the project specific settings from the shared
Verilog code. Another way I could have done this was to set it as a
parameter that is visible on the top-level MHS file of the EDK project.
However, if I change the variable, I'd have to re-generate the
simulation models in EDK, which takes more time. Commenting out the
above vlog line the .do script is much faster.

Thanks again for both of your assistance.

NN

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