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  #1 (permalink)  
Old 05-16-2009, 04:32 PM
wzab
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Default Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python withoutXilinx DLLs?

Hi,

I need to use the standard BSCAN_SPARTAN3 or BSCAN_VIRTEX4 component
to access user logic in an embedded system, which hopefully is able
to run the libusb-driver, but will not run the Xilinx libraries used
e.g. by the standard tcljtag.tcl script.

Additionally the access is needed from thy Python language, not from the
Tcl.

Has anybody succeeded to access the BSCAN_xxxx components from the raw
JTAG library (libusb-driver, or OpenOCD, or openwince), which in turn
may be used by the Python software?
--
TIA & Regards,
Wojtek
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  #2 (permalink)  
Old 05-16-2009, 04:49 PM
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Default Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python withoutXilinx DLLs?

On May 16, 5:32*pm, wzab <[email protected]> wrote:
> Hi,
>
> I need to use the standard BSCAN_SPARTAN3 or BSCAN_VIRTEX4 component
> to access user logic in an embedded system, which hopefully is able
> to run the libusb-driver, but will not run the Xilinx libraries used
> e.g. by the standard tcljtag.tcl script.
>
> Additionally the access is needed from thy Python language, not from the
> Tcl.
>
> Has anybody succeeded to access the BSCAN_xxxx components from the raw
> JTAG library (libusb-driver, or OpenOCD, or openwince), which in turn
> may be used by the Python software?
> --
> TIA & Regards,
> Wojtek


sure we use in our own software all the time

but you can not use xilinx usb cables, as the protocol is not public

Antti

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  #3 (permalink)  
Old 05-16-2009, 05:32 PM
wzab
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Default Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python withoutXilinx DLLs?

Dnia 16.05.2009 [email protected] <[email protected]>
wrote:
>
> sure we use in our own software all the time
>
> but you can not use xilinx usb cables, as the protocol is not public
>

I may be wrong, but it seems to me, that the libusb-driver allows to access
the Xilinx cable as well.
Certainly I need to make some experiments, but it seems, that the
libusb-driver allows to access also the Xilinx cable...

And the DEBUG version option allows to trace the protocol fully, so I don't
think it is a big problem.

I know it can be done, but I'd like to know if anybody has already done it
and may/want to share the results...
--
Thanks,
Wojtek
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  #4 (permalink)  
Old 05-16-2009, 06:07 PM
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Default Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python withoutXilinx DLLs?

On May 16, 6:32*pm, wzab <[email protected]> wrote:
> Dnia 16.05.2009 [email protected] <[email protected]>
> wrote:
>
> > sure we use in our own software all the time

>
> > but you can not use xilinx usb cables, as the protocol is not public

>
> I may be wrong, but it seems to me, that the libusb-driver allows to access
> the Xilinx cable as well.
> Certainly I need to make some experiments, but it seems, that the
> libusb-driver allows to access also the Xilinx cable...
>
> And the DEBUG version option allows to trace the protocol fully, so I don't
> think it is a big problem.
>
> I know it can be done, but I'd like to know if anybody has already done it
> and may/want to share the results...
> --
> Thanks,
> Wojtek


well you CAN of connect to xilinx usb cable, but you need to RE the
protocol

Antti
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  #5 (permalink)  
Old 05-17-2009, 04:15 PM
wzab
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Default Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python withoutXilinx DLLs?

Hi,

I've succeeded to access the BSCAN_SPARTAN3 without any Xilinx software.
I've used the libusb-driver: http://rmdir.de/~michael/xilinx/
and urJTAG: http://urjtag.org/

The BSCAN_SPARTAN3 has been instantiated as follows in my VHDL code:
[...]
signal jt_shift, jt_tck, jt_update, jt_tdi, jt_tdo, jt_capture, jt_tck2,
jt_sel1, jt_sel2, jt_rst, jt1, jt2, jt3 : std_ulogic := '0';
[...]
BSS3_1 : BSCAN_SPARTAN3
port map (CAPTURE => jt_capture,
DRCK1 => jt_tck,
DRCK2 => jt_tck2,
RESET => jt_rst,
SEL1 => jt_sel1,
SEL2 => jt_sel2,
SHIFT => jt_shift,
TDI => jt_tdi,
UPDATE => jt_update,
TDO1 => jt_tdo,
TDO2 => jt_tdi);
process (jt_tck)
begin -- process
if jt_tck'event and jt_tck = '1' then -- rising clock edge
jt1 <= jt_tdi;
jt2 <= jt1;
jt3 <= jt2;
jt_tdo <= jt3;
end if;
end process;

process (jt_update)
begin -- process
if jt_update'event and jt_update = '1' then -- rising clock edge
led(3) <= jt3;
led(2) <= jt2;
led(1) <= jt1;
end if;
end process;
[...]

I have compiled libusb-driver and urjtag, and run it as follows:
$ PATH="/home/user/urjtag/bin":$PATH \
LD_PRELOAD="/home/user/xilinx-usb-driver/libusb-driver.so" jtag

Then from the jtag prompt I have run the following commands (I have used the
Xilinx SPARTAN-3E Starter Kit via the USB platform cable):

cable xpc_ext
detect
part 0
instruction BYPASS
part 1
instruction BYPASS
part 2
register UR 3
instruction USER1 000010 UR
instruction USER1
shift ir
dr 111
shift dr

I could set the required LED pattern with the sequences like
dr 100
shift dr
dr 001
shift dr

In fact, to get the whole thing working, I had to introduce a small
modification in the urJTAG files.

In the original urJTAG, the "detect" command returned the following results:
jtag> detect
IR length: 22
Chain length: 3
Device Id: 00000110111001011110000010010011 (0x0000000006E5E093)
Manufacturer: Xilinx
Part(0): XC2C64-VQ44
Stepping: 0
Filename:
/home/user/urjtag/share/urjtag/xilinx/xc2c64a-vq44/xc2c64a-vq44
Device Id: 11110101000001000110000010010011 (0x00000000F5046093)
Manufacturer: Xilinx
Part(1): xcf04s
Unknown stepping!
Device Id: 00000001110000100010000010010011 (0x0000000001C22093)
Manufacturer: Xilinx
Part(2): xc3s500e_fg320
Stepping: 0
Filename:
/home/user/urjtag/share/urjtag/xilinx/xc3s500e_fg320/xc3s500e_fg320
chain.c(149) Part 1 without active instruction
chain.c(200) Part 1 without active instruction
chain.c(149) Part 1 without active instruction
jtag>

And then I was not able to set the INSTRUCTION for the part 1:

jtag> part 0
jtag> instruction BYPASS
jtag> part 1
jtag> instruction BYPASS
instruction: unknown instruction 'BYPASS'
jtag>

I have found that the SETTINGS file for the xcf04s
( /home/user/urjtag/xilinx/xcf04s/SETTINGS ) contains the following entry:
# bits 31-28 of the Device Identification Register
0000 xcf04s 0

This bits in my xcf04s are set to '1's, so I've added the following line:
( PLEASE BEWARE, THAT I HAVE DONE IT WITHOUT ANY KNOWLEDGE AND UNDERSTANDING
WHAT THIS LINE IS FOR :-(. I JUST WANTED TO BYPASS THE xcf04s. PROBABLY
ACCESSING ANY OTHER FUNCTIONS OF xcf04S REQUIRES MORE REASONABLE ADJUSTMENT
OF "SETTINGS" FILE. OTHERWISE THE CHIP MAY BE POSSIBLY DAMAGED)

# bits 31-28 of the Device Identification Register
0000 xcf04s 0
1111 xcf04s f

After this change detection worked correctly:
jtag> detect
IR length: 22
Chain length: 3
Device Id: 00000110111001011110000010010011 (0x0000000006E5E093)
Manufacturer: Xilinx
Part(0): XC2C64-VQ44
Stepping: 0
Filename:
/home/xl/urjtag/bin/share/urjtag/xilinx/xc2c64a-vq44/xc2c64a-vq44
Device Id: 11110101000001000110000010010011 (0x00000000F5046093)
Manufacturer: Xilinx
Part(1): xcf04s
Stepping: f
Filename: /home/xl/urjtag/bin/share/urjtag/xilinx/xcf04s/xcf04s
Device Id: 00000001110000100010000010010011 (0x0000000001C22093)
Manufacturer: Xilinx
Part(2): xc3s500e_fg320
Stepping: 0
Filename:
/home/xl/urjtag/bin/share/urjtag/xilinx/xc3s500e_fg320/xc3s500e_fg320

And I was able to set the xcf04s in the BYPASS mode:
jtag> part 0
jtag> instruction BYPASS
jtag> part 1
jtag> instruction BYPASS
jtag>

So now, the "only" thing I have to add are the Python bindings for urJTAG...
--
Regards,
Wojtek
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  #6 (permalink)  
Old 05-17-2009, 08:28 PM
wzab
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Default Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python withoutXilinx DLLs?

Hi,

Creating of Python bindings for urJTAG appeared to be too complicated :-(
(hopefully it will be possible to change it in the future).
Therefore I have created a quick (but SLOOOW in operation) solution,
based on interactive communication with urJTAG shell via the Python
pexpect module.
You can find the code here:
http://groups.google.com/group/alt.s...ff14bdf020776#
(remember to access the message via the "show original" option).
--
Regards,
Wojtek

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