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Old 10-09-2007, 04:32 PM
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Default 8B/10B Xilinx Paper

Hello newsgroup,

I am trying to understand the Xilinx reference design (XAPP391: Design
of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)).
When performing the functional simulation (which is included in the
download files) the error detection signal of the decoder becomes
active
on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE
and 0x2BE.

The testbench provided with the design connects the encoder
and the decoder, so that only legal 10bit words get into the decoder.
8bit --> enc --> 10bit --> dec --> 8bit

So why does these errors occur ? Has someone
already used that reference design and has met
difficulties in simulation or real hardware implementation ?

Thank you.
Best regards
Andre

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  #2 (permalink)  
Old 10-09-2007, 05:55 PM
mk
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Default Re: 8B/10B Xilinx Paper

On Tue, 09 Oct 2007 08:32:09 -0700, "[email protected]" <[email protected]>
wrote:

>Hello newsgroup,
>
>I am trying to understand the Xilinx reference design (XAPP391: Design
>of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)).
>When performing the functional simulation (which is included in the
>download files) the error detection signal of the decoder becomes
>active
>on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE
>and 0x2BE.
>
>The testbench provided with the design connects the encoder
>and the decoder, so that only legal 10bit words get into the decoder.
>8bit --> enc --> 10bit --> dec --> 8bit
>
>So why does these errors occur ? Has someone
>already used that reference design and has met
>difficulties in simulation or real hardware implementation ?
>

Is it possible that there is error verification conditions in the
testbench, ie. the errors are injected on purpose to see if error
checking works?
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  #3 (permalink)  
Old 10-10-2007, 08:06 AM
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Posts: n/a
Default Re: 8B/10B Xilinx Paper

On 9 Okt., 18:55, mk <kal*@dspia.*comdelete> wrote:
> On Tue, 09 Oct 2007 08:32:09 -0700, "[email protected]" <[email protected]>
> wrote:
>
>
>
>
>
> >Hello newsgroup,

>
> >I am trying to understand the Xilinx reference design (XAPP391: Design
> >of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)).
> >When performing the functional simulation (which is included in the
> >download files) the error detection signal of the decoder becomes
> >active
> >on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE
> >and 0x2BE.

>
> >The testbench provided with the design connects the encoder
> >and the decoder, so that only legal 10bit words get into the decoder.
> >8bit --> enc --> 10bit --> dec --> 8bit

>
> >So why does these errors occur ? Has someone
> >already used that reference design and has met
> >difficulties in simulation or real hardware implementation ?

>
> Is it possible that there is error verification conditions in the
> testbench, ie. the errors are injected on purpose to see if error
> checking works?- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -


I think that there is no error injection in the testbench. In the
error cases
the 8bit words presented by the decoder are OK.


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  #4 (permalink)  
Old 10-11-2007, 10:15 AM
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Default Re: 8B/10B Xilinx Paper

When changing the order of 8bit words (integer) into the encoder from
a)...236 - 237 - 238 - 239... to
b)...236 - 8 - 238 ... (encoded word of 8 has
negative
disparity)


the error detection module does not show an error for
the 0x1C7 (encoded word of 238).


The question is how to find the error in the encoder description ...


Rgds
Andre

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