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  #1 (permalink)  
Old 11-15-2006, 07:55 PM
logjam
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Default 8080 FSGA model in an FPGA

I would like to eventually make an 8080 out of Field Solderable Gate
Arrays. (trasistors)

First, I want to design the whole thing in an FPGA for logic proofing
There will be a LOT of circuit boards required for this and I want to
limit failure... My idea was to create small macro blocks that emulate
standard TTL chips and use those TTL chips (or customized versions) to
build the processor.

Any recomendations on how to proceed? I want to make the core I/O
compatible with the 8080, which means full status signal support and a
2 phase clock.

Thanks,
Grant

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  #2 (permalink)  
Old 11-15-2006, 09:25 PM
PeteS
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Default Re: 8080 FSGA model in an FPGA

Jon Elson wrote:
>
>
> logjam wrote:
>
>> I would like to eventually make an 8080 out of Field Solderable Gate
>> Arrays. (trasistors)
>>
>> First, I want to design the whole thing in an FPGA for logic proofing
>> There will be a LOT of circuit boards required for this and I want to
>> limit failure... My idea was to create small macro blocks that emulate
>> standard TTL chips and use those TTL chips (or customized versions) to
>> build the processor.
>>
>> Any recomendations on how to proceed? I want to make the core I/O
>> compatible with the 8080, which means full status signal support and a
>> 2 phase clock.
>>
>>

> Logjam sounds like a good name for this project. A google search turns up
> it was built from 6000 transistors. Well, each transistor is going to
> need a
> drain (or collector) resistor at the least. What will you use for
> gating, diodes?
> Add at least one more resistor to pull up the diode gate's output to the
> transistor's
> gate or base. Well, assuming most of the transistors are for 2-input
> gates, now
> we have 6000 times 5 components (2 diodes, 2 res, one trans) = 30,000
> components.
> Does this still sound practical?
>
> I don't know the specific logic design for the 8080 other than it was
> some form
> of NMOS. So, it may be that this can be done in a lot less than 6000
> transistors
> if you use diode gates.
>
> Anyway, it should be fairly easy to design the CPU for FPGA implementation.
> I'd forget the TTL component emulation, and use either VHDL or Verilog,
> or maybe
> one of the RTL synthesis tools. These are able to specify a CPU very
> concisely.
>
> Jon
>


I seem to recall from the distant past that the 8080 (some versions)
used depletion load; i.e. a depletion mode device with gate tied to
source instead of a resistive load. Not that it reduces the components
(an in fact adds a pin per active transistor).

Cheers

PeteS
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  #3 (permalink)  
Old 11-15-2006, 09:55 PM
Jon Elson
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Default Re: 8080 FSGA model in an FPGA



logjam wrote:

>I would like to eventually make an 8080 out of Field Solderable Gate
>Arrays. (trasistors)
>
>First, I want to design the whole thing in an FPGA for logic proofing
>There will be a LOT of circuit boards required for this and I want to
>limit failure... My idea was to create small macro blocks that emulate
>standard TTL chips and use those TTL chips (or customized versions) to
>build the processor.
>
>Any recomendations on how to proceed? I want to make the core I/O
>compatible with the 8080, which means full status signal support and a
>2 phase clock.
>
>

Logjam sounds like a good name for this project. A google search turns up
it was built from 6000 transistors. Well, each transistor is going to
need a
drain (or collector) resistor at the least. What will you use for
gating, diodes?
Add at least one more resistor to pull up the diode gate's output to the
transistor's
gate or base. Well, assuming most of the transistors are for 2-input
gates, now
we have 6000 times 5 components (2 diodes, 2 res, one trans) = 30,000
components.
Does this still sound practical?

I don't know the specific logic design for the 8080 other than it was
some form
of NMOS. So, it may be that this can be done in a lot less than 6000
transistors
if you use diode gates.

Anyway, it should be fairly easy to design the CPU for FPGA implementation.
I'd forget the TTL component emulation, and use either VHDL or Verilog,
or maybe
one of the RTL synthesis tools. These are able to specify a CPU very
concisely.

Jon

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  #4 (permalink)  
Old 11-15-2006, 10:55 PM
Jim Granville
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Default Re: 8080 FSGA model in an FPGA

logjam wrote:
> I would like to eventually make an 8080 out of Field Solderable Gate
> Arrays. (trasistors)


Why ?!

>
> First, I want to design the whole thing in an FPGA for logic proofing
> There will be a LOT of circuit boards required for this and I want to
> limit failure... My idea was to create small macro blocks that emulate
> standard TTL chips and use those TTL chips (or customized versions) to
> build the processor.
>
> Any recomendations on how to proceed? I want to make the core I/O
> compatible with the 8080, which means full status signal support and a
> 2 phase clock.


Do you also want this voltage compatible ?
What is the target of this project ?

-jg


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  #5 (permalink)  
Old 11-15-2006, 11:50 PM
logjam
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Default Re: 8080 FSGA model in an FPGA

> we have 6000 times 5 components (2 diodes, 2 res, one trans) = 30,000
> components.
> Does this still sound practical?


Not practical, but fun! I have a 88x40 inch display made out of 19,008
T 1 3/4 LEDs for example...

> Anyway, it should be fairly easy to design the CPU for FPGA implementation.
> I'd forget the TTL component emulation, and use either VHDL or Verilog,
> or maybe
> one of the RTL synthesis tools. These are able to specify a CPU very
> concisely.


Would there be a simple way of generating some sort of human
understandable information that would help generate a schematic?

Thanks,
Grant

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  #6 (permalink)  
Old 11-15-2006, 11:55 PM
logjam
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Default Re: 8080 FSGA model in an FPGA

> Do you also want this voltage compatible ?
> What is the target of this project ?


I want to be able to use it in place of a real 8080. I don't care
about the 12 and -5v power supply. The whole project is just for fun.

The reason I thought TTL would be a good place to start is because of
the AMD 2901 9080 emulator book. Also, if standard TTL devices were
replicated using transistors then each "module" of the processor could
possibly be tested with an IC tester.

I figure it will have a few thousand LEDs too. Like an LED for every
register, microcode bit, etc.

Grant

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  #7 (permalink)  
Old 11-16-2006, 01:34 AM
JJ
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Posts: n/a
Default Re: 8080 FSGA model in an FPGA


logjam wrote:
> > Do you also want this voltage compatible ?
> > What is the target of this project ?

>
> I want to be able to use it in place of a real 8080. I don't care
> about the 12 and -5v power supply. The whole project is just for fun.
>
> The reason I thought TTL would be a good place to start is because of
> the AMD 2901 9080 emulator book. Also, if standard TTL devices were
> replicated using transistors then each "module" of the processor could
> possibly be tested with an IC tester.
>
> I figure it will have a few thousand LEDs too. Like an LED for every
> register, microcode bit, etc.
>
> Grant


Since this is for fun and not practicality you could try and google for
home built computers using TTL or better still CMOS etc. There really
are a few souls out there that have built TTL boxes in this day and
age. I almost contemplated this 20yrs ago for a PDP8 with a real core
stack and transistors but I found some sense.

Also you could actually reverse engineer a real 8080 with a modest
microscope, the details are pretty clear after you remove the
passivation, a dead device will be okay too. It only used IIRC 1 layer
of metal, poly, active area and hidden poly diff contacts. I did some
reverse engineering on this part so its no so bad.

As for circuit design the 8080 was an NMOS design with mostly dynamic
logic and some sparing use of static logic (not sure) so the schematic
could be recovered with some basic knowledge of chip design circa
1975. Adison Wesley had a couple of old 1984 VLSI books that describe
all the basic NMOS tricks used in the day, you would need to follow
gate clocking, bootstrapping, cheap C latches etc. The clocks would
have been used to strobe latches and flops and logic might well have
been merged.

The 8085 might be a whole lot easier being IIRC all static (and 5V) so
you wouldn't find as much mind boggling circuit tricks, just logic.
IIRC it was mostly pin compatible so would be alot easier.

I would atleast stick to TTL compatible CMOS parts to save yourself SI
hell.

John Jakson
transputer guy

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  #8 (permalink)  
Old 11-16-2006, 02:17 AM
Tim
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Posts: n/a
Default Re: 8080 FSGA model in an FPGA


JJ wrote...
>
> logjam wrote:
>> > Do you also want this voltage compatible ?
>> > What is the target of this project ?

>>
>> I want to be able to use it in place of a real 8080. I don't care
>> about the 12 and -5v power supply. The whole project is just for fun.
>>
>> The reason I thought TTL would be a good place to start is because of
>> the AMD 2901 9080 emulator book. Also, if standard TTL devices were
>> replicated using transistors then each "module" of the processor could
>> possibly be tested with an IC tester.
>>
>> I figure it will have a few thousand LEDs too. Like an LED for every
>> register, microcode bit, etc.
>>
>> Grant

>
> Since this is for fun and not practicality you could try and google for
> home built computers using TTL or better still CMOS etc. There really
> are a few souls out there that have built TTL boxes in this day and
> age. I almost contemplated this 20yrs ago for a PDP8 with a real core
> stack and transistors but I found some sense.


Many years ago, on a visit to Amdahl I saw a complete 470 built with
wire-wrapped TTL. How about doing the 8080 with a giant wire-wrap board of
CMOS PALs. One PAL per "logical chunk," with lots of outputs reserved for
the LEDs. It might even be possible to buy an old wire-wrap X-Y frame on
eBay. Maybe cook up a standard module with a little PAL, LEDs, some drivers,
I/O pins, and JTAG. You would be the defining case for JTAG's ability to
program hundreds of PALs in series ;-)

And good luck with the clock tree...

Tim


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  #9 (permalink)  
Old 11-16-2006, 02:50 AM
Jim Granville
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Posts: n/a
Default Re: 8080 FSGA model in an FPGA

logjam wrote:
>>Do you also want this voltage compatible ?
>>What is the target of this project ?

>
>
> I want to be able to use it in place of a real 8080. I don't care
> about the 12 and -5v power supply. The whole project is just for fun.


I saw someone did a 4004, as plug-able device.

So do you want to run some real 8080 SW on this ?
Over what memory bus/sizes ?

>
> The reason I thought TTL would be a good place to start is because of
> the AMD 2901 9080 emulator book.


Why not follow that line, with a bit-slice emulation of the 8080 ?

A very good starting point there, would be to take something like
the open source Mico8 8 bit CPU from lattice, and tweak/tune it to
allow a SW emulation layer of 8080, as you will have MHz to spare

> Also, if standard TTL devices were
> replicated using transistors then each "module" of the processor could
> possibly be tested with an IC tester.


If you have one available. Transistors I'd take as a dead-end,
unless you have a soldering fetish !

Tiny logic maybe, but that's going to be more a PCB design problem, not
an 8080 design problem, and you will chew $$ on the PCBs

CPLDs, or FPGAs are probably the best level to do this project.
Low enough that you CAN get to every logic element, but still
high enough to be affordable, small and low power.

>
> I figure it will have a few thousand LEDs too. Like an LED for every
> register, microcode bit, etc.


Or, a TV/VGA output that emulates such LEDs ?

-jg

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  #10 (permalink)  
Old 11-16-2006, 06:39 AM
scott moore
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Default Re: 8080 FSGA model in an FPGA

Jon Elson wrote:

> Anyway, it should be fairly easy to design the CPU for FPGA implementation.
> I'd forget the TTL component emulation, and use either VHDL or Verilog,
> or maybe
> one of the RTL synthesis tools. These are able to specify a CPU very
> concisely.
>
> Jon
>


Or use the one that already exists on http://www.opencores.org :-)

Scott Moore
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  #11 (permalink)  
Old 11-16-2006, 09:30 AM
David R Brooks
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Default Re: 8080 FSGA model in an FPGA

JJ wrote:
> logjam wrote:
>>> Do you also want this voltage compatible ?
>>> What is the target of this project ?

>> I want to be able to use it in place of a real 8080. I don't care
>> about the 12 and -5v power supply. The whole project is just for fun.
>>
>> The reason I thought TTL would be a good place to start is because of
>> the AMD 2901 9080 emulator book. Also, if standard TTL devices were
>> replicated using transistors then each "module" of the processor could
>> possibly be tested with an IC tester.
>>
>> I figure it will have a few thousand LEDs too. Like an LED for every
>> register, microcode bit, etc.
>>
>> Grant

>
> Since this is for fun and not practicality you could try and google for
> home built computers using TTL or better still CMOS etc. There really
> are a few souls out there that have built TTL boxes in this day and
> age. I almost contemplated this 20yrs ago for a PDP8 with a real core
> stack and transistors but I found some sense.


See my Simplex page http://members.iinet.com.au/~daveb/simplex/simplex.html
links to a webring of such designs.
>
> Also you could actually reverse engineer a real 8080 with a modest
> microscope, the details are pretty clear after you remove the
> passivation, a dead device will be okay too. It only used IIRC 1 layer
> of metal, poly, active area and hidden poly diff contacts. I did some
> reverse engineering on this part so its no so bad.
>
> As for circuit design the 8080 was an NMOS design with mostly dynamic
> logic and some sparing use of static logic (not sure) so the schematic
> could be recovered with some basic knowledge of chip design circa
> 1975. Adison Wesley had a couple of old 1984 VLSI books that describe
> all the basic NMOS tricks used in the day, you would need to follow
> gate clocking, bootstrapping, cheap C latches etc. The clocks would
> have been used to strobe latches and flops and logic might well have
> been merged.
>

Back in the 70's, all kinds of dirty logic tricks were used: the
circuitry was not the clean, canonical stuff you are forced to build
using TTL or other stock logic family.
Dynamic gates for instance: first clock charges the node, then the logic
optionally discharges it on the next clock.
If you are building with discrete transistors, bear in mind that the
standard discrete flipflop was a master-slave design, with the master
implemented in just such dynamic logic (as 2 capacitors).
By transistors, I assume you mean bipolars? This precludes another MOS
logic dodge: the pass gate. This is a series switch, which exploits the
symmetry of a basic MOS device (source & drain are interchangeable).

A good reference would be Mead & Conway's "Introduction to VLSI
Systems", Addison Wesley, 1984.
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  #12 (permalink)  
Old 11-16-2006, 03:07 PM
John Adair
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Default Re: 8080 FSGA model in an FPGA

Without looking at a 8080 datasheet properly we may have a platform for you
to play on if that is what you need. Craignell1/2/3 info and maybe even some
pictures will be up our website next week, or possibly week after that if we
get delayed. They are in manufacture currently. You may have to do a minor
rewire using stripboard for the power pins as Craignell modules follow
standard 5V DIL pinout for which I think the 8080 varies.

Before anyone asks the module uses 5V as power I/P, pins are 5V tolerant,
and it even has 5V pullups to make 5V CMOS levels to the outside world. It's
designed as an obsolete component replacement but equally good for hobby or
student electronic projects with 0.1 inch leg pitch. Standard offerings will
have 100K gate Spartan-3E on-board but 250K and 500K gate varieties can also
be made.

John Adair
Enterpoint Ltd. - Home of Craignell1/2/3. The DIL Spartan-3E Development
Module.
http://www.enterpoint.co.uk

"logjam" <[email protected]> wrote in message
news:[email protected] ups.com...
>I would like to eventually make an 8080 out of Field Solderable Gate
> Arrays. (trasistors)
>
> First, I want to design the whole thing in an FPGA for logic proofing
> There will be a LOT of circuit boards required for this and I want to
> limit failure... My idea was to create small macro blocks that emulate
> standard TTL chips and use those TTL chips (or customized versions) to
> build the processor.
>
> Any recomendations on how to proceed? I want to make the core I/O
> compatible with the 8080, which means full status signal support and a
> 2 phase clock.
>
> Thanks,
> Grant
>



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  #13 (permalink)  
Old 11-16-2006, 03:47 PM
rickman
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Posts: n/a
Default Re: 8080 FSGA model in an FPGA

logjam wrote:
> > Do you also want this voltage compatible ?
> > What is the target of this project ?

>
> I want to be able to use it in place of a real 8080. I don't care
> about the 12 and -5v power supply. The whole project is just for fun.
>
> The reason I thought TTL would be a good place to start is because of
> the AMD 2901 9080 emulator book. Also, if standard TTL devices were
> replicated using transistors then each "module" of the processor could
> possibly be tested with an IC tester.
>
> I figure it will have a few thousand LEDs too. Like an LED for every
> register, microcode bit, etc.


I guess you can build an 8080 out of TTL logic blocks, but that will
not be the way it was designed in the NMOS technology of the day. When
I was in high school we were given an old (even for 1967) weather
computer that did not use ICs. Each logic function; NAND gate, NOR
gate, FF, etc; was made from transistors using RTL logic technology.
But the main thing to consider was that it was made in modules about 2"
square with edge pin connectors based on standard functions. If you
are going to build your own 8080 from transistors, it is going to be
large and you need to modularize it to make it practical.

Other than very low level primatives such as AND/OR/FF, you might
consider building large functions such as registers or perhaps even a
22V10 type module. It could be designed to provide the full
functionality of a 22V10 with jumpers or even just solder bridges for
programming. I'd be willing to bet you can make an 8080 out of just a
few dozen 22V10 modules. With today's packaging technology, this could
be smaller than the 2" square modules in the old weather computer my
high school had.

What will you be using for memory, diode arrays? The weather computer
used a magnetic drum as its memory. Timing is everything!

BTW, if you want to start a little smaller, you might consider the
8008. It had similar registers, but used an 8 bit multiplexed
address/memory bus and was quite a bit smaller inside with fewer
instructions. But then that would give you a pretty limited CPU
wouldn't it? ;^)

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  #14 (permalink)  
Old 11-16-2006, 04:41 PM
Tim
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Default Re: 8080 FSGA model in an FPGA

rickman:
> I guess you can build an 8080 out of TTL logic blocks, but that will
> not be the way it was designed in the NMOS technology of the day. When
> I was in high school we were given an old (even for 1967) weather
> computer that did not use ICs. Each logic function; NAND gate, NOR
> gate, FF, etc; was made from transistors using RTL logic technology.
> But the main thing to consider was that it was made in modules about 2"
> square with edge pin connectors based on standard functions.


As I recall, that's how DEC got started.

If you decide to go with the 2900, Mick and Brick has a complete
worked-through design, though not for an 8080. The book is worth buying
(second hand only) for the alliterative authors' names.


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  #15 (permalink)  
Old 11-16-2006, 04:43 PM
Gerhard Hoffmann
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Default Re: 8080 FSGA model in an FPGA

On 16 Nov 2006 07:47:35 -0800, "rickman" <[email protected]> wrote:

>I guess you can build an 8080 out of TTL logic blocks, but that will
>not be the way it was designed in the NMOS technology of the day. When


There was a Schottky TTL chip slice implementation of the 8080 by Plessey.
Size was several DoubleEuro-Cards and speed abt. 20 MHz(?), probably
for the military market or who else could afford it.
Name was Miproc or sth. like that.

regards, Gerhard

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  #16 (permalink)  
Old 11-16-2006, 09:18 PM
Jon Elson
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Default Re: 8080 FSGA model in an FPGA



PeteS wrote:

>
> I seem to recall from the distant past that the 8080 (some versions)
> used depletion load; i.e. a depletion mode device with gate tied to
> source instead of a resistive load. Not that it reduces the components
> (an in fact adds a pin per active transistor).
>

So do these depletion loads count in the 8000 transistors? Then, the
8080 function could
maybe be performed by 4000 active devices and 4000 resistors. (Im sort
of thinking that
it was 8000 amplifying transistors in the count, 4000 just seems too
low, as you'd need
2 for every FF, and the 8080 actually had a lot of registers, for the time.)

Jon

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  #17 (permalink)  
Old 11-16-2006, 09:19 PM
Jon Elson
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Default Re: 8080 FSGA model in an FPGA



logjam wrote:

>>we have 6000 times 5 components (2 diodes, 2 res, one trans) = 30,000
>>components.
>>Does this still sound practical?
>>
>>

>
>Not practical, but fun! I have a 88x40 inch display made out of 19,008
>T 1 3/4 LEDs for example...
>
>
>
>>Anyway, it should be fairly easy to design the CPU for FPGA implementation.
>>I'd forget the TTL component emulation, and use either VHDL or Verilog,
>>or maybe
>>one of the RTL synthesis tools. These are able to specify a CPU very
>>concisely.
>>
>>

>
>Would there be a simple way of generating some sort of human
>understandable information that would help generate a schematic?
>
>

Yes, RTL was used as a descriptive tool for YEARS before there ever was
a synthesis
tool that accepted it.

Jon

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  #18 (permalink)  
Old 11-17-2006, 08:14 PM
PeteS
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Posts: n/a
Default Re: 8080 FSGA model in an FPGA

Jon Elson wrote:
>
>
> PeteS wrote:
>
>>
>> I seem to recall from the distant past that the 8080 (some versions)
>> used depletion load; i.e. a depletion mode device with gate tied to
>> source instead of a resistive load. Not that it reduces the components
>> (an in fact adds a pin per active transistor).
>>

> So do these depletion loads count in the 8000 transistors? Then, the
> 8080 function could
> maybe be performed by 4000 active devices and 4000 resistors. (Im sort
> of thinking that
> it was 8000 amplifying transistors in the count, 4000 just seems too
> low, as you'd need
> 2 for every FF, and the 8080 actually had a lot of registers, for the
> time.)
>
> Jon
>

The depletion load devices did not count in the 'transistor' count -
they were load devices - active resistors, really

Cheers

PeteS
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  #19 (permalink)  
Old 11-17-2006, 10:27 PM
JJ
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Default Re: 8080 FSGA model in an FPGA


Jon Elson wrote:
> PeteS wrote:
>
> >
> > I seem to recall from the distant past that the 8080 (some versions)
> > used depletion load; i.e. a depletion mode device with gate tied to
> > source instead of a resistive load. Not that it reduces the components
> > (an in fact adds a pin per active transistor).
> >

> So do these depletion loads count in the 8000 transistors? Then, the
> 8080 function could
> maybe be performed by 4000 active devices and 4000 resistors. (Im sort
> of thinking that
> it was 8000 amplifying transistors in the count, 4000 just seems too
> low, as you'd need
> 2 for every FF, and the 8080 actually had a lot of registers, for the time.)
>
> Jon


Every transistor counts whether it is a logic pull down (enhancemenet)
or load (depletion). or clocked pass gate or even any capacitors which
are usually free in area, its always distinct mos gate area. A
depletion transitor is usually used as a constant current source rather
than resistor, but as a resistor if the gate has fixed voltage.
Typically for all static logic I would expect 3 logic and 1 load device
on avg, but in this case most logic was precharged and conditionally
discharged. Only the register flops had to be static.

Since it had a 12v supply, it may have not had any depletion device
loads, using long thin enhacment t's s as loads, mucho area and power
and poor speed. The 8085, Z80 definitely had depletion and hidden
poly-diff contacts to simplify everthing.

I did have the schematic for the datapath area and thats about 30% of
the chip. IIRC maybe 8-10 registers included umdocumented, each was
probably a 4t asymetric cross couple with an extra t to read and and t
for write. An ALU bit slice is probably 20-30 t's so 1 datapath
bitslice is probably <100 devices so <1000 for the whole math area..

Remember that t logic (see Mead Conway) can do alot for a few devices.
2e1d devices makes a 2 input nor or nand or poor mans xor and the ALU
used only a few per bit. The carry was a precharged manchester pass
gate with conditional discharge, the P,G terma probably reused a mux
box function generator (a bit like a LUT) that also did the logic
operations.

Also the whole thing was state sequential, no pipelining so many cycles
used to do trivial operations. The entire schematc could have easily
been drawn on 1 large sheet of paper if need be.

John Jakson
transputer guy

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  #20 (permalink)  
Old 11-20-2006, 11:24 PM
Jon Elson
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Posts: n/a
Default Re: 8080 FSGA model in an FPGA



JJ wrote:

>Every transistor counts whether it is a logic pull down (enhancemenet)
>or load (depletion). or clocked pass gate or even any capacitors which
>are usually free in area, its always distinct mos gate area. A
>depletion transitor is usually used as a constant current source rather
>than resistor, but as a resistor if the gate has fixed voltage.
>Typically for all static logic I would expect 3 logic and 1 load device
>on avg, but in this case most logic was precharged and conditionally
>discharged. Only the register flops had to be static.
>
>Since it had a 12v supply, it may have not had any depletion device
>loads, using long thin enhacment t's s as loads, mucho area and power
>and poor speed. The 8085, Z80 definitely had depletion and hidden
>poly-diff contacts to simplify everthing.
>
>I did have the schematic for the datapath area and thats about 30% of
>the chip. IIRC maybe 8-10 registers included umdocumented, each was
>probably a 4t asymetric cross couple with an extra t to read and and t
>for write. An ALU bit slice is probably 20-30 t's so 1 datapath
>bitslice is probably <100 devices so <1000 for the whole math area..
>
>Remember that t logic (see Mead Conway) can do alot for a few devices.
>2e1d devices makes a 2 input nor or nand or poor mans xor and the ALU
>used only a few per bit. The carry was a precharged manchester pass
>gate with conditional discharge, the P,G terma probably reused a mux
>box function generator (a bit like a LUT) that also did the logic
>operations.
>
>Also the whole thing was state sequential, no pipelining so many cycles
>used to do trivial operations. The entire schematc could have easily
>been drawn on 1 large sheet of paper if need be.
>
>
>

Even as a gate-level schematic it would be a pretty busy sheet of paper!
I hope the OP is not going to go through with this project. There is
Seymour
Cray's first computer at the Computer History Museum, a big box with
hundreds of small boards he etched by hand in his garage. Of course, he
got to sell the thing to the Navy when he finished it. The OP is going
to go
through the same level of effort, but he won't make a dime on it.

I'm reminded of the guy in Germany, I think, who built a digital clock using
vacuum tubes for all the amplifying elements. Even using some very tricky
designs with multi-grid tubes, it was a monster with over 100 tubes.

Jon

Jon

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  #21 (permalink)  
Old 11-21-2006, 12:53 AM
Ray Andraka
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Default Re: 8080 FSGA model in an FPGA

Jon Elson wrote:


Some people have way too much time on their hands!
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  #22 (permalink)  
Old 11-21-2006, 09:22 AM
Grant Stockly
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Default Re: 8080 FSGA model in an FPGA

Ray Andraka wrote:
> Jon Elson wrote:
>
>
> Some people have way too much time on their hands!


I want to use the transistor board set as part of a possible computer
kit / electronics trainer. I have just completed the Altair Kit
reproduction that I've been working on for 9 months as a hobby. If I
can stick with it and get that done on my time off, I think a
transistor 8080 would be easy.

http://www.altairkit.com
http://cgi.ebay.com/ws/eBayISAPI.dll...m=250052265051

Any way, I guess I would be happy if the transistor computer were
instruction set compatible AND timing compatible. I really am not
concerned about how the computer is constructed at the transistor
level, but I want the status signals the same and the instruction set
cycle count to be the same. If a program depends on a software delay
loop, I would want it to be equal.

Maybe I'm trying to attempt too much. I think my best bet is to
reasearch the 9080 emulator by AMD and duplicate that. Its possible I
could rewrite the microcode to include status bit states. Who knows...

With this new information, does anyone see a different easier path? Or
am I still just plain crazy? I won't be making any transistor
8080s until I'm out from under all the investments in the Altair
project!

Grant

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  #23 (permalink)  
Old 11-21-2006, 01:40 PM
rickman
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Posts: n/a
Default Re: 8080 FSGA model in an FPGA

Grant Stockly wrote:
> Ray Andraka wrote:
> > Jon Elson wrote:
> >
> >
> > Some people have way too much time on their hands!

>
> I want to use the transistor board set as part of a possible computer
> kit / electronics trainer. I have just completed the Altair Kit
> reproduction that I've been working on for 9 months as a hobby. If I
> can stick with it and get that done on my time off, I think a
> transistor 8080 would be easy.
>
> http://www.altairkit.com
> http://cgi.ebay.com/ws/eBayISAPI.dll...m=250052265051
>
> Any way, I guess I would be happy if the transistor computer were
> instruction set compatible AND timing compatible. I really am not
> concerned about how the computer is constructed at the transistor
> level, but I want the status signals the same and the instruction set
> cycle count to be the same. If a program depends on a software delay
> loop, I would want it to be equal.
>
> Maybe I'm trying to attempt too much. I think my best bet is to
> reasearch the 9080 emulator by AMD and duplicate that. Its possible I
> could rewrite the microcode to include status bit states. Who knows...
>
> With this new information, does anyone see a different easier path? Or
> am I still just plain crazy? I won't be making any transistor
> 8080s until I'm out from under all the investments in the Altair
> project!


If you are just trying to build a trainer of some sort, wouldn't it be
easier to build a simulation that could show all the internal states?
It has got to be easier to do a simulation than a construction project
from transistors or even from CPLDs.

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  #24 (permalink)  
Old 11-21-2006, 08:59 PM
Grant Stockly
Guest
 
Posts: n/a
Default Re: 8080 FSGA model in an FPGA

> If you are just trying to build a trainer of some sort, wouldn't it be
> easier to build a simulation that could show all the internal states?
> It has got to be easier to do a simulation than a construction project
> from transistors or even from CPLDs.


I guess its because I'm in Alaska? The largest state in the union
mentality causes me to want to build a computer from transistors?

I just find it so interesting that it can be done. Why not make a kit!
Wouldn't a second box under the altair with a few hundred lights
be neat to watch?

I really want to build a computer from relays, and even priced out some
nice ones on e-bay, but I am concerned about how long it would last
before failing...

Grant

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  #25 (permalink)  
Old 11-21-2006, 09:28 PM
Frank Buss
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Posts: n/a
Default Re: 8080 FSGA model in an FPGA

Grant Stockly wrote:

> I really want to build a computer from relays, and even priced out some
> nice ones on e-bay, but I am concerned about how long it would last
> before failing...


If it is clocked with <10 Hz, like the first computer of the world:

http://irb.cs.tu-berlin.de/~zuse/Kon...echner_Z3.html

it should last very long with modern relais.

--
Frank Buss, [email protected]
http://www.frank-buss.de, http://www.it4-systems.de
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