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Old 04-25-2006, 07:44 PM
bad synchrounous assignment
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Default 116 warnings... successive approximation register using both phases of clock by spliting them

after compiling my project...116 warnings came ... i m new to VHDL..
gotta submit within 24 hrs
HELP>>SOS>>SOS

hello thr

hi! i am stuck up pretty bad with my project and need your immediate
assistance within 24hrs...... i have successive approximation register
using VHDL and simulated it in Altera: Quartus 2 5.0 web edition.. now
i have no errors but 116 warnings of all sorts plus output waveform is
not what i was expecting either... now I tell you somethin regarding
how it shud work and if you can please see what all you can do to make
it run fine.... this is S.O.S.... save me man..........
I use a component called clock generator that provides me with two
clocks both in phase opposition to each other (VHDL description is
included in project).... so basically what i tried to do is to decrease
the number of clock cycles tht normally takes for successive
approximation by almost half.... from single clock I derived two clocks
and divided the entire logic into two halves each running alternatively
one after another so that by using both the halves of incoming clock I
am able to get result in half the time... but anyways
its all useless till the shit starts giving me correct outputs....
Well best of luck to you:

feel free for any other information......

VHDL code for clockgenerator is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clkgen is
Port ( clk : in std_ulogic;
nclk: out std_ulogic;
pclk : out std_ulogic
);
end clkgen;

architecture Behavioral of clkgen is
begin
nclk <= clk nand clk;
pclk <= clk and '1';
end Behavioral;

VHDL CODE FOR SAR(main project) IS

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sar_b is
Port ( clk, Cin, Em, Rm : in std_ulogic;
sample: out std_ulogic := '0';
eoc: out std_ulogic := '0';
I: out std_ulogic_vector(7 downto 0) := "00000000";
O: out std_ulogic_vector(7 downto 0) := "00000000");
end sar_b;
architecture behavioral of sar_b is
signal check: BOOLEAN;
signal nc,pc: std_ulogic;
signal d:std_ulogic_vector(0 to 7) := "00000000";
component clkgen is
port (clk : in std_ulogic;
nclk : out std_ulogic;
pclk : out std_ulogic
);
end component clkgen;
begin
c1: clkgen port map(clk,nc,pc);--positive clock(pn)&negative clk(nc)
process (Em, Rm, nc, pc,Cin, d)
variable temp: integer := 0;
begin
if Em = '1' then
if Rm = '1' then
I<="00000000";
O<="00000000";
d<="00000000";
if pc = '1' then
temp:=temp+1;
if temp = 1 then
d(7)<='1';
I<="10000000";
sample<=i(7);
elsif temp = 2 then
d(6)<=Cin;
d(5)<='1';
I<=(d(7),d(6),'1',others=>'0');
elsif temp = 3 then
d(4)<=Cin;
d(3)<='1';
I<=(d(7),d(6),d(5),d(4),'1','0','0','0');
elsif temp = 4 then
d(2)<= Cin;
d(1)<= '1';
I<=(d(7),d(6),d(5),d(4),d(3),d(2),'1','0');
elsif temp = 5 then
d(0)<=Cin;
I<=D;
end if;
end if;
elsif nc = '1' then
if temp = 1 then
d(7)<=Cin;
d(6)<='1';
I<=(d(7),'1',others=>'0');
elsif temp = 2 then
d(5)<=Cin;
d(4)<='1';
I<=(d(7),d(6),d(5),'1', others=>'0');
elsif temp = 3 then
d(3)<=Cin;
d(2)<='1';
I<=(d(7),d(6),d(5),d(4),d(3),'1','0','0');
elsif temp = 4 then
d(1)<= Cin;
d(0)<= '1';
I<=(d(7),d(6),d(5),d(4),d(3),d(2),d(1),'0');
elsif temp = 5 then
O<=d;
eoc<='1';
end if;
end if;
end if;

end process;
end behavioral;

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  #2 (permalink)  
Old 04-25-2006, 08:51 PM
Sylvain Munaut
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Default Re: 116 warnings... successive approximation register using bothphases of clock by spliting them

bad synchrounous assignment wrote:
> after compiling my project...116 warnings came ... i m new to VHDL..
> gotta submit within 24 hrs
> HELP>>SOS>>SOS
>
> hello thr
>
> hi! i am stuck up pretty bad with my project and need your immediate
> assistance within 24hrs......


May I suggest to hire in emergency a consultant that you're gonna pay
$$$$ to work out your problem thru the night.


Sylvain
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