FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > DSP

DSP comp.dsp newsgroup, mailing list

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 12-09-2003, 06:30 AM
Bhanu Prakash Reddy
Guest
 
Posts: n/a
Default Core with Static design

Hi Grp,

I was going through a DSP core, which says that the core is "Fully
Static design that enables clock frequency down to DC". How different
is this design compared to other cores? wat are its advantages.

Regards,
Bhanu Prakash
Reply With Quote
  #2 (permalink)  
Old 12-09-2003, 07:25 AM
glen herrmannsfeldt
Guest
 
Posts: n/a
Default Re: Core with Static design

Bhanu Prakash Reddy wrote:

> Hi Grp,


> I was going through a DSP core, which says that the core is "Fully
> Static design that enables clock frequency down to DC". How different
> is this design compared to other cores? wat are its advantages.


Many intel designs use dynamic logic, such as dynamic memory for
registers. The minimum clock rate for the 8086 is something like 2MHz.

For most people it doesn't make a difference, but some hardware
debugging is easier if you can control the clock.

-- glen

Reply With Quote
  #3 (permalink)  
Old 12-09-2003, 02:39 PM
Jim Thomas
Guest
 
Posts: n/a
Default Re: Core with Static design

Bhanu Prakash Reddy wrote:
> Hi Grp,
>
> I was going through a DSP core, which says that the core is "Fully
> Static design that enables clock frequency down to DC". How different
> is this design compared to other cores? wat are its advantages.


You can achieve low power with these devices by slowing the clock down -
or even stopping it for a sort of "homemade" idle mode. Transistors in
digital logic use power mostly when they are switching, so the slower
the clock, the less switching, and thus, the less power used.

Back in the good ol' days, I implemented "partial" wait states on a
fully static ADSP2100. This DSP used a 4x input clock, and I needed
just a little more access time for some remote memory. A "real" wait
state would have added an entire additional cycle, and back then, that
seemed like a lot. I squashed the input clock at just the right time
instead, extending the access time:

regular memory read
_ _ _ _
clk _| |_| |_| |_| |_
_________ ____
rd |___|

read with "partial" wait state using sqashed clock
_ _ _ _
clk _| |_| |_| |_____| |_
_________ ____
rd |_______|

It worked beautifully, but in retrospect, it was a lot of work for not
much gain.

--
Jim Thomas Principal Applications Engineer Bittware, Inc
[email protected] http://www.bittware.com (703) 779-7770
To mess up a Linux box, you need to work at it; to mess up your Windows
box, you just need to work on it. - Scott Granneman

Reply With Quote
  #4 (permalink)  
Old 12-09-2003, 06:08 PM
Jerry Avins
Guest
 
Posts: n/a
Default Re: Core with Static design

Jim Thomas wrote:

...


> Back in the good ol' days, I implemented "partial" wait states on a
> fully static ADSP2100. This DSP used a 4x input clock, and I needed
> just a little more access time for some remote memory. A "real" wait
> state would have added an entire additional cycle, and back then, that
> seemed like a lot. I squashed the input clock at just the right time
> instead, extending the access time:
>
> regular memory read
> _ _ _ _
> clk _| |_| |_| |_| |_
> _________ ____
> rd |___|
>
> read with "partial" wait state using sqashed clock
> _ _ _ _
> clk _| |_| |_| |_____| |_
> _________ ____
> rd |_______|
>
> It worked beautifully, but in retrospect, it was a lot of work for not
> much gain.


Don't sell it short. How many cycles at today's clock rates would that
time saving represent?

This works even with dynamic registers. Fortunately, refresh time isn't
all that critical.

Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ

Reply With Quote
  #5 (permalink)  
Old 12-09-2003, 06:09 PM
Jerry Avins
Guest
 
Posts: n/a
Default Re: Core with Static design

Jim Thomas wrote:

...


> Back in the good ol' days, I implemented "partial" wait states on a
> fully static ADSP2100. This DSP used a 4x input clock, and I needed
> just a little more access time for some remote memory. A "real" wait
> state would have added an entire additional cycle, and back then, that
> seemed like a lot. I squashed the input clock at just the right time
> instead, extending the access time:
>
> regular memory read
> _ _ _ _
> clk _| |_| |_| |_| |_
> _________ ____
> rd |___|
>
> read with "partial" wait state using sqashed clock
> _ _ _ _
> clk _| |_| |_| |_____| |_
> _________ ____
> rd |_______|
>
> It worked beautifully, but in retrospect, it was a lot of work for not
> much gain.


Don't sell it short. How many cycles at today's clock rates would that
time saving represent?

This works even with dynamic registers. Fortunately, refresh time isn't
all that critical.

Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Xilinx PCIe endpoint core minimalistic design [email protected] FPGA 2 07-25-2007 05:05 PM
Available: Detailed RISC CPU IP Core Design Documentation John Gulbrandsen VHDL 0 04-10-2007 05:17 PM
Available: Detailed RISC CPU IP Core Design Documentation John Gulbrandsen FPGA 0 04-10-2007 05:17 PM
Available: Detailed RISC CPU IP Core Design Documentation John Gulbrandsen Verilog 0 04-10-2007 05:17 PM
Can I unstantiate IBERT core in a V4FX design? MM FPGA 0 10-24-2006 10:13 PM


All times are GMT +1. The time now is 06:17 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved