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  1. Data Structure Viewer
  2. Webpack sees 2 clocks when there is only one
  3. Win2k service packs for running Xilinx tools
  4. Virtex "Virtual VCC"
  5. Q: async flip-flop reset by a signal from a different clock domain
  6. Re: Design fits XC9536 but not XC9536XL
  7. ANN: Confluence 0.6
  8. Pad-to-pad hold time
  9. Re: FPGA advantage 5.3 & unisim package
  10. inconsistent DCM delay from TRCE report ?
  11. Atmel CPLD programming tools
  12. a quick searching problem
  13. Re: speeding up quartus
  14. FPGA for a Newcomer
  15. Re: Xilinx virtex II DCM CLKFX output not working
  16. Re: Xilinx virtex II DCM CLKFX output not working
  17. DDR-ram interface (xapp200)
  18. from Altera to Xilinx
  19. Xilinx Webpack ISE and Verilog-2001?
  20. Re: speeding up quartus
  21. SheerPower 4GL -- Beyond BASIC V3.4
  22. Synopsys search path
  23. reconfiguration time
  24. Virtex-II RocketIO: Serial ATA?
  25. Re: Clocking in a virtex 2 without using the clock trees : questions
  26. Virtex-E power trace
  27. Re: clock management on SPARTAN2
  28. Compilation error
  29. I am new and I want to help
  30. Upgrading OS or WebPack
  31. Re: Quartus II and fixing hold timing
  32. Re: Quartus II and fixing hold timing
  33. Re: Size does matter
  34. Post synthesis(PAR) Simln in Xilinx WEbPack 5.2: Port Mismatch error
  35. Re: Size does matter
  36. Re: Gates Counting?
  37. Need help: getting 3.1i Coregen working on P4-system
  38. Re: How to find the intersection of two vectors?
  39. Re: Spartan-IIE LVDS?
  40. Excalibur - lpm_syncram
  41. Xilinx Error Msg- Help Required
  42. Error Generate Statement
  43. Xilinx ISE WebPack 5.2 & VHDL : wait synthesis
  44. OT: Offshore engineering
  45. Confusing Xilinx Webpack warning
  46. Re: Does Xilinx Webpack 5.2 work on WinNT SP6?
  47. Tool chains that take in EDIF 2 0 0/LPM 2 1 0
  48. Re: Using 3rd Party IP Cores...
  49. Re: Does Xilinx Webpack 5.2 work on WinNT SP6?
  50. Re: Spartan 3 support in Webpack
  51. Re: FPGAs: basic question: two-level AND-OR vs. two-level OR-AND
  52. Re: power saving condition test ?
  53. Re: Using 3rd Party IP Cores...
  54. Memory map for Nios
  55. Re: Questions in Altera FPGA MegaCore Compact-PCI Configuration Spaceunder Windows NT
  56. Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
  57. Re: Parallel Port EPP in FPGA
  58. How to use EAB in Altera FPGA?
  59. 6th MAPLD: End of Early Registration and Program Announcement
  60. Re: Xuart Lite Linux driver
  61. Block ram simulation
  62. Re: ERROR:iMPACT:1210
  63. Re: "ML300 Embedded" Mapping Help
  64. Re: Gates Counting?
  65. model sim block ram sim
  66. retiming with Synplify Pro
  67. JTAG programmers
  68. Conflict found between ActiveHDL6.1 and ModelSim SE
  69. Multiple device configuration using local update over ethernet
  70. Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
  71. Re: LCD and step-up DC-DC converter.
  72. Re: Nios Ethernet Development Kit Problems
  73. Re: Xuart Lite Linux driver
  74. Patent granted for "system on a chip" framework?
  75. Re: LCD and step-up DC-DC converter.
  76. Re: Gates Counting?
  77. how to protect own IP in Xilinx ISE
  78. Re: Design fits XC9536 but not XC9536XL
  79. More VHDL issues..
  80. Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
  81. interface with 860
  82. Re: DDS question. How to generate a square from a sine wave?
  83. Re: 5 volt tolerant Xilinx parts
  84. Re: 5 volt tolerant Xilinx parts
  85. Re: Altera Nios 3: Using Interface To User Logic Problem
  86. Re: 'Virtual Grounds'
  87. Clock recovery chip for electirical interfacing of LXT6155 to SPECTRA chip
  88. Re: Parallel Port EPP in FPGA
  89. Multiple clock generations
  90. Re: Showing my ignorance of VHDL again...
  91. Re: reconfiguration VirtexE via JTAG (full or partial)
  92. Re: reconfiguration VirtexE via JTAG (full or partial)
  93. Re: Gates Counting?
  94. Re: 5 volt tolerant Xilinx parts
  95. opencores.org - Question on project licensing?
  96. Re: beginner
  97. Re: Pricing question....
  98. Re: Size does matter
  99. Re: Size does matter
  100. Re: Showing my ignorance of VHDL again...
  101. Re: Size does matter
  102. Re: two questions
  103. Question: String matching with CAM?
  104. Downloading into XCV600
  105. Re: binary to BCD assistance
  106. Re: PLL / DPLL phase question
  107. Synthesisable fixed-point arithmetic package
  108. Re: binary to BCD assistance
  109. Re: Multi Cycle path and False paths
  110. GL85 synthesizable code
  111. Relative placement constraints in VHDL for Virtex multipliers
  112. XST fails to recognize FSM with registered outputs
  113. Phase / frequency detector types
  114. Digital Design with just one clock at one edge
  115. Re: what are libraries for??
  116. Digital Root circuit using tree of 4-bit CLA's with Cout fed into Cin
  117. Re: I/Os with Cypress chip
  118. Re: edge card connectors and high speed design
  119. Re: An All Digital Phase Lock Loop
  120. Re: free downloadable VLSI softwares
  121. Combinational logic and gate delays - Help
  122. Re: edge card connectors and high speed design
  123. Quartus VHDL problem with aggregate and type cast
  124. Re: Quartus warning in NUMERIC_STD.vhd
  125. XML for VHDL documention and structural description of Hardware SoC
  126. PROM JTAG download cable for Xilinx Spartan II + Webpack
  127. how can I use a signal defined in one Architecture to another Architecture
  128. Make file ...........Help Please
  129. Re: clock management on SPARTAN2
  130. Synplify and then Quartus
  131. How to change Read Only Constraint to Read-Write
  132. cascaded DLL's in VirtexE, routing problems
  133. Xilinx price question
  134. Leonardo changes name of lpm megafunction
  135. Re: Books
  136. Re: Cyclone vs Spartan-3
  137. Re: scaling fixed point fft
  138. Re: clock management on SPARTAN2
  139. Re: About BRAM in VirtexII
  140. Re: About BRAM in VirtexII
  141. phase noise in NCO
  142. Copy Altera Config EPC2 via JTAG?
  143. Re: Dynamic Reconfiguration, Contentions
  144. Re: eCOS port for NIOS
  145. std_logic_vector type port doesn't work after synthesis.
  146. wired downloading bitstream to spartan2
  147. Re: Interfaces in Handelc
  148. Re: [DLL usage Virtex/Spartan-II] HowTo drive CLKDV Div 2 off Chip
  149. Re: How to Tristate!!! when not reading
  150. Re: User Core OPB Problem (EDK3.2)
  151. Rant mode ON
  152. July 9, 2003 Anti-government Demonstration in Iran
  153. ISE 5.1/5.2 Error
  154. GSR
  155. Re: Altera licenses
  156. Beta sites needed
  157. Re: Pulse stretching
  158. CPSR register
  159. Re: Exceptional conditions on XST.
  160. Nios bash acting bizzar
  161. Problem with user defined logicinterface in Nios
  162. Re UART troubles solved - THANKS Mike, Peter, and Philip!!
  163. spartan2e block ram error
  164. Spartan XL Tool Support
  165. control R/C servos with FPGAs
  166. Re: QuartusII software licencing
  167. test
  168. What About CPLD Standardization ?
  169. Re: Excel and FPGA's
  170. Spartan2E + PCI
  171. Re: PC-104 dev Boards
  172. CRACKED SOFTWARE(CAD,CAE,CAM,EDA,PCB,GIS,CNC,FEA,CFD)
  173. Xilinx:CAM
  174. Re: Excel and FPGA's
  175. hidden remap failed
  176. division
  177. Re: Starter Question and Opinion on VHDL
  178. test
  179. information required
  180. DCM usage question
  181. Re: Everything need a reset?
  182. constraints, etc
  183. okay what am I missing??? Please
  184. Re: Everything need a reset?
  185. Difficulty with OPB bus and user IP
  186. Quartus II 3.0 Release & Web Edition Download Links
  187. Questions about Design Compiler.
  188. ACEX (EP1K) Power-Up Current
  189. Re: xilinx and web pack questions newbe
  190. Re: Parallel processing
  191. Re: cyclone on pci?
  192. Using Quarus to create SVF files?
  193. Spartan-3 availability
  194. create JAM-File for Xilinx device
  195. RE:can you please post a summary of your findings to the group?
  196. [DLL Virtex/Spartan-II] Which is the right feedback in x1 and x2 Appl
  197. check one two check check
  198. What a fascinating board!
  199. ARM+FPGA
  200. post-PAR simulation model
  201. XPLA3 vs. MAX3000A
  202. Re: Cyclone vs Spartan-3
  203. Re: VHDL & OV6620 CMOS camera
  204. Re: How to get 27MHz from 10 MHz in FPGA???
  205. New FPGA RISC C-NIT
  206. NIOS tutorial for the Stratix1S10
  207. Re: Xlilin xc9572XL Default register values
  208. Virtex 2Pro, ML300, VP2PDK, EDK, etc..
  209. Process variable setup times and propogations
  210. Re: PCB Problem
  211. Re: How to get 27MHz from 10 MHz in FPGA???
  212. Discrepancy in CLB Usage Report
  213. Re: Does anyone know about hardware implementaions of the SVD ?
  214. Re: Everything need a reset?
  215. Re: ASIC divider in FPGA?
  216. Re: defparam LUT_4
  217. Combining Distributed RAM and Block RAM
  218. Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
  219. Looking for DIMM format FPGA board
  220. Re: why so many problems Xilinx ?
  221. Fixed point signed multiplication algorithm
  222. Re: projects for beginners
  223. Re: 48bit adder won't fit
  224. Why not DDR in FPGAs?
  225. Re: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or BUFGP symbol "u1" (output signal=u1), IPAD-IBUFG should only be LOC'd to GCLKIOB site."
  226. Regarding NRZ
  227. FPGA Editor and Xilinx ISE 5.1i
  228. Need help in capturing serial data using FPGA and ethernet interface
  229. Re: Cyclone vs Spartan-3
  230. VHDL variable setup and propogations
  231. Re: memory
  232. ARM C/C++ compiler independent of OS
  233. Re: Xilinx ML300 JTAG Configuration Problem
  234. VirtexII bitstream relocation
  235. Celoxica feedback
  236. Re: Quartus produces wrong parameters for Stratix PLL
  237. Re: Suitable motherboard for Spartan-IIE PCI design
  238. Re: fpga video evaluation board
  239. Re: Cyclone vs Spartan-3
  240. Re: Xilinx ML300 JTAG Configuration Problem
  241. Re: Cyclone vs Spartan-3
  242. Re: Asynchronous RESET?
  243. device selection for game system
  244. EDK/XPS/Virtex2Pro - TFT core not avaialble
  245. NAND flash file
  246. Re: why so many problems Xilinx ?
  247. Re: NgdBuild:477 - clock net xx has non-clock connections
  248. Re: Xlilin xc9572XL Default register values
  249. Seriell Decoder possibly in ABEL for Lattice CPLD
  250. Re: SPARTAN-3 vs. VIRTEX-II